EPM1270F256I5N Low-Power MAX II CPLD with 1270 Logic Elements and 212 I/O Field Programmable Gate Array
EPM1270F256I5N MAX® II instant-on, non-volatile CPLDs are based on a 0.18-µm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. These devices offer high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability (ISP), EPM1270F256I5N MAX II devices are designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset (POR) and sequencing control, and device configuration control.
| Operating Supply Voltage | 2.5 V, 3.3 V |
| Number of Macrocells | 980 Macrocell |
| Number of I/Os | 212 I/O |
| Minimum Operating Temperature | -40°C |
| Maximum Operating Temperature | +85°C |
| Maximum Operating Frequency | 304 MHz |
| Propagation Delay - Max | 6.2 ns |
| Memory Type | Flash |
| Moisture Sensitive | Yes |
| Number of Logic Array Blocks - LABs | 127 |
| Number of Logic Elements | 1270 |
| Operating Supply Current | 55 mA |
| Supply Voltage - Max | 3.6 V |
| Supply Voltage - Min | 2.375 V |
| Total Memory | 8192 bit |
| Unit Weight | 1.500 g |
- Low-cost, low-power CPLD
- Instant-on, non-volatile architecture
- Standby current as low as 25 µA
- Provides fast propagation delay and clock-to-output times
- Provides four global clocks with two clocks available per logic array block (LAB)
- UFM block up to 8 Kbits for non-volatile storage
- MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V
- MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels
- Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors
- Schmitt triggers enabling noise tolerant inputs (programmable per pin)
- I/Os are fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz
- Supports hot-socketing
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990
- ISP circuitry compliant with IEEE Std. 1532
- Video processing: Capable of high-speed video data processing, making it suitable for applications such as video capture and image processing.
- Communications: Supports a variety of communication protocols and interfaces, making it suitable for applications in areas such as network communications and wireless communications.
- Industrial control: Featuring high performance and low power consumption, it is suitable for applications requiring long-term operation, such as industrial control.
| Part Number | Package |
|---|---|
| WLAN7201HCZ | HVQFN-40 |
| KW45B41Z52AFPBR | HVQFN40 |
| KW45Z41083AFPBR | HVQFN40 |
| BTS6302UJ | 16-HVQFN |
| TEF8232EN1/N1/ZTZ | WFBGA165 |
| TEF8232EN1/N1/ZUZ | WFBGA165 |
| AFSC5G35E38T2 | 26-LQFN |
| SDINBDG4-64G-XI1 | BGA |
| SDINBDA6-128G-ZA | TFBGA-153 |
| SDINBDG4-8G-XA | BGA |
| SDINBDA6-128G-XA | TFBGA-153 |
| SDINBDG4-64G-I1 | BGA |
| SDINBDG4-16G-XA | BGA |
| SDINBDA6-256G-XA | TFBGA-153 |
| SDINBDA6-32G-XA | TFBGA-153 |
| SDINBDG4-32G-XA | BGA |
| SDINBDG4-8G-ZA | BGA |
| SDINBDA4-128G | BGA |
| SDINBDG4-32G-ZA | BGA |
| SDINBDA4-32G | BGA |
| SDINBDG4-8G-ZAT | BGA |
| SDINBDG4-16G-XI1 | BGA |
| SDINBDG4-64G-XA | BGA |
| SDINBDA6-64G-XA | TFBGA-153 |
| SDINDDH6-64G-I | BGA |
| SDINBDA6-64G-ZA | TFBGA-153 |
| SDINBDA6-32G-ZA | TFBGA-153 |
| SDINDDH6-256G-I | BGA |
| SDINBDG4-64G-H | BGA |
| SDINDDH6-32G-XI | BGA |
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