Flash Programmable System Device with 8032 Microcontroller Core

FEATURES SUMMARY

■ The µPSD3200 Family combines a Flash PSD architecture with an 8032 microcontroller core The µPSD3200 Family of Flash PSDs features dual banks of Flash memory, SRAM, general purpose I/O and programmable logic, supervisory functions and access via USB, I2C, ADC, DDC and PWM channels, and an on-board 8032 microcontroller core, with two UARTs, three 16-bit Timer/Counters and one External Interrupt. As with other Flash PSD families, the µPSD3200 Family is also in-system programmable (ISP) via a JTAG ISP interface.

■ Large 8 KByte SRAM with battery back-up option

■ Dual bank Flash memories

– 128 KByte or 256 KByte main Flash memory

– 32 KByte secondary Flash memory

■ Content Security

– Block access to Flash memory

SUMMARY DESCRIPTION

■ Dual bank Flash memories

– Concurrent operation, read from memory one while erasing and writing the other. In-Application Programming (IAP) for remote updates

– Large 128 KByte or 256 KByte main Flash memory for application code, operating systems, or bit maps for graphic user interfaces – Large 32 KByte secondary Flash memory divided in small sectors. Eliminate external EEPROM with software EEPROM emulation

– Secondary Flash memory is large enough for sophisticated communication protocol (USB) during IAP while continuing critical system tasks

■ Large SRAM with battery back-up option

– 8 KByte SRAM for RTOS, high-level languages, communication buffers, and stacks

■ Programmable Decode PLD for flexible address mapping of all memories

– Place individual Flash and SRAM sectors on any address boundary

– Built-in page register breaks restrictive 8032 limit of 64 KByte address space

– Special register swaps Flash memory segments between 8032 “program” space and “data” space for efficient In-Application Programming

Figure 2. µPSD3200 Family Functional Modules

HOT PRODUCTS