USRP-LW N310 | SDR USRP Software Defined Radio Ethernet Port Low Latency
Ethernet port series USRP-LW N310
The USRP-LW N310 is a networked software-defined radio (SDR) that provides reliability and fault tolerance for deployment in large-scale and distributed wireless systems.
The USRP-LW N310 is one of the highest channel counts on the SDR market today, with a dual AD9371 RFIC transceiver on the RF front end that provides four transceiver channels in a half-width RU package. Each channel provides up to 100 MHz of instantaneous bandwidth and covers an extended frequency range of 10 MHz to 6 GHz. The baseband processor uses the Xilinx Zynq-7100 SoC to provide large user-programmable FPGAs for real-time and low-latency processing, as well as dual-core ARM CPUs for standalone operations. Supports 1 GbE, 10 GbE and Aurora interfaces via dual SPF+ ports, which can be implemented to the host PC or High-throughput IQ streams for FPGA coprocessors. The flexible synchronization architecture supports clock reference, PPS time reference, external LO input, and GPSDO, enabling high channel count MIMO systems. The USRP-LW N310 simplifies the control and management of radio networks by introducing the ability to perform tasks remotely, such as debugging, updating software, rebooting, factory reset, self-test, host PC/ARM debugging, and monitoring system health.
Includes:
- USRP-LW N310
- RJ45 Ethernet cable
- SFP+ to RJ45 adapter
- Micro-USB cable
- MicroSD card
- power supply
Main features:
| • Reliable and fault-tolerant deployment |
• AD9371 configurable clock reference frequency: 122.88MHz, 125MHz, 153.6 MHz |
| • Remote management capabilities | |
| • Frequency coverage from 10MHz to 6GHz | • 16 bit ADC, 14 bit DAC |
| • Instantaneous bandwidth of up to 100M per channel | • Dual SPF+ ports (Gigabit Ethernet, 10 Gigabit Ethernet, Aurora). |
| • Support 4 send 4 receipts at the same time | • Dual-core ARM Cortex-A9 CPU 800 MHz |
| • Transceiver filter banks | • Built-in Xilinx Zynq-7100 SoC FPGA |
| • Support external RX LO, TX LO input | • Supports external clock reference and PPS time reference |
| • RFNoC FPGA development framework | • Supports standalone (embedded) or host-based (network) operations |
| • 1 Type A USB host port | • UHD3.11.0 or later support |
| • Built-in custom linux | • 1 micro-USB port (serial console, JTAG) |
| • Support for GNU Radio |
Baseband processor:
The USRP-LW N310 baseband processor uses Xilinx's zynq-7100 SOC, which provides a rich set of programmable FPGAs for real-time demanding and low-latency processing as well as dual-core ARM CPU stand-alone operation. Users can deploy applications on pre-installed Linux embedded operating systems, or use high-speed interfaces such as Gigabit Ethernet Host, 10 Gigabit Ethernet.
synchronous:
The USRP-LW N310 has a flexible reference clock design architecture that supports external PPS, clock reference time reference, external LO input, and gpsdo, which facilitates high channel count MIMO Implementation of the system.
USRP-LW N310 technical data:
|
Parameter category |
numeric value |
unit |
Parameter category |
numeric value |
unit |
|
reception |
launch |
||||
|
Number of channels |
4 |
- |
Number of channels |
4 |
- |
|
Independent tuning |
2 |
- |
Independent tuning |
2 |
- |
|
L0 shared pairs |
2 |
- |
L0 shared pairs |
2 |
- |
|
Gain range |
-40 ~ 30 |
dB |
The gain range is 10MHz to 300MHz |
-30 ~ 25 |
dB |
|
|
|
|
|||
|
Gain stepping |
1 |
dB |
300MHz~6GHz |
-30 ~ 20 |
dB |
|
Maximum input power |
-15 |
dBm |
Gain stepping |
1 |
dB |
|
Filter bank |
10 ~ 430 |
MHz |
Filter bank |
10 ~ 300 |
MHz |
|
430 ~ 600 |
300 ~ 723.17 |
||||
|
600 ~ 1050 |
723.17 ~ 1623.17 |
||||
|
1050 ~ 1600 |
1623.17 ~ 3323.17 |
||||
|
1600 ~ 2100 |
3323.17 ~ 6000 |
||||
|
2100 ~ 2700 |
|
||||
|
2700 ~ 6000 |
|
||||
|
An external local oscillator frequency range can be input |
0.6 ~ 8 |
GHz |
An external local oscillator frequency range can be input |
0.6 ~ 8 |
GHz |
|
TX/RX switching time |
140 |
μs |
TX/RX switching time |
140 |
μs |
|
Conversion and clock performance |
power |
||||
|
Sample rate |
122.88,125,153.6 |
MS/s |
DC voltage input |
12,7 |
V,A |
|
ADC resolution |
16 |
bits |
power consumption |
50-80 |
W |
|
DAC resolution |
14 |
bits |
Physical properties |
||
|
Minimum frequency step 122.88MS/s |
7.32 |
Hz |
size |
425×220×45 |
mm |
|
125MS/s |
7.45 |
Hz |
|||
|
153.6MS/s |
9.15 |
Hz |
|||
|
GPSDO frequency stability is not locked |
0.1 |
ppm |
weight |
3.8 |
kg |
|
GPSDO PPS relative to UTC accuracy |
<8 |
ns |
Operating environment requirements |
||
|
GPSDO latency stability |
<+/-50 |
μs |
Stable range of operation |
0 ~ 50 |
°C |
|
3 |
hours |
||||
|
25 |
°C |
Storage temperature range |
-40 ~ 70 |
°C |
|
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