Universal Software Radio Peripheral, USRP-LW N321,Compatible with ETTUS USRP N321

Product Overview

USRP-LW N321 is a network software-defined radio that provides reliability and fault tolerance for deployment in large-scale and distributed wireless systems. This is a high-performance SDR that uses a unique RF design to provide 2 RX and 2 TX channels in a half-width RU size. Each channel can provide up to 200 MHz instantaneous bandwidth and cover an extended frequency range from 3 MHz to 6 GHz. The baseband processor uses Xilinx Zynq-7100 SoC to deliver a large user-programmable FPGA for real-time, low-latency processing, and a dual-core ARM CPU for independent operation. It has two SPF+ ports and one QSFP+ port, supports 1 GbE, 10 GbE and Aurora interfaces, and can stream high-throughput IQ to the host PC or FPGA coprocessor. The flexible synchronization architecture supports 10 MHz clock reference, PPS time reference, external TX and RX LO input and GPSDO, which can realize phase coherent MIMO test platform. The USRP-LW N321 has the ability to import any TX and RX LO with a supported frequency higher than 450 MHz, providing a way to build a large-scale, phase-coherent MIMO test platform suitable for various advanced wireless research topics. In addition, USRP-LW N321 allows to export TX and RX LO in Star configuration to multiple other USRP-LW N321 devices. USRP-LW N321 utilizes UHD's latest software development to simplify the control and management of multiple devices on the network, and has unique remote management tasks, such as debugging, updating software, restarting, resetting to factory state and monitoring system operation situation.

Main Features

• Reliable and fault-tolerant deployment
• Remote management capabilities
• Stand-alone (embedded) or host-based (network stream) operation
• Fully integrated and assembled (USRP N321 does not support exchangeable daughter cards)
• 3 MHz to 6 GHz extended frequency range
• Up to 200 MHz instantaneous bandwidth per channel
• 2RX,2TX
• RX,TX Filter bank
• 14-bit ADC, 16-bit DAC
• Master clock rate:200,245.76250 MS / s
• Xilinx Zynq-7100 SoC
• Dual-core ARM Cortex-A9 800 MHz CPU
• QSFP+ port
• 2 SFP+ ports (1 Gigabit Ethernet, 10 Gigabit Ethernet, Aurora)
• RJ45(1 GbE)
• Clock reference
• PPS time reference
• External RX LO, TX LO input and output ports
• Built-in GPSDO
• 1 type A USB host port
• 1 micro-USB port (serial console, JTAG)
• Watchdog timer
• OpenEmbedded Linux
• USRP hardware driver (UHD3.15.0.0 or higher) and open source software API version
• RFNoC™ FPGA Development Framework

Technical index:

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