PC16552DVX/NOPB UART Interface ICs ASYNCHRON RCVR/TRANS W/ FIFO

General Description

The PC16552D is a dual version of the PC16550D Universal Asynchronous Receiver Transmitter (UART) The two serial channels are completely independent except for a common CPU interface and crystal input On power-up both channels are functionally identical to the 16450 Each channel can operate with on-chip transmitter and receiver FIFOs (FIFO mode) to relieve the CPU of excessive software overhead In FIFO mode each channel is capable of buffering 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) of data in both the transmitter and receiver All the FIFO control logic is on-chip to minimize system overhead and maximize system efficiency

Signalling for DMA transfers is done through two pins per

channel (TXRDY and RXRDY) The RXRDY function is mul-

tiplexed on one pin with the OUT 2 and BAUDOUT func- tions The CPU can select these functions through a new register (Alternate Function Register)
Each channel performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters re- ceived from the CPU The CPU can read the complete status of each channel at any time Status information re- ported includes the type and condition of the transfer opera- tions being performed by the DUART as well as any error conditions (parity overrun framing or break interrupt)

The DUART includes one programmable baud rate genera- tor for each channel Each is capable of dividing the clock input by divisors of 1 to (216 b 1) and producing a 16 c clock for driving the internal transmitter logic Provisions are also included to use this 16 c clock to drive the receiver logic The DUART has complete MODEM-control capability and a processor-interrupt system Interrupts can be pro- grammed to the user’s requirements minimizing the com- puting required to handle the communications link

The DUART is fabricated using National Semiconductor’s advanced M2CMOSTM