28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

Power Management Features:

• Run: CPU on, Peripherals on

• Idle: CPU off, Peripherals on

• Sleep: CPU off, Peripherals off

• Ultra Low 50nA Input Leakage

• Run mode Currents Down to 11 μA Typical

• Idle mode Currents Down to 2.5 μA Typical

• Sleep mode Current Down to 100 nA Typical

• Timer1 Oscillator: 900 nA, 32 kHz, 2V

• Watchdog Timer: 1.4 μA, 2V Typical

• Two-Speed Oscillator Start-up

Flexible Oscillator Structure:

• Four Crystal modes, up to 40 MHz

• 4x Phase Lock Loop (PLL) – Available for Crystal and Internal Oscillators

• Two External RC modes, up to 4 MHz

• Two External Clock modes, up to 40 MHz

• Internal Oscillator Block: - Fast wake from Sleep and Idle, 1 μs typical - 8 use-selectable frequencies, from 31 kHz to 8 MHz - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL - User-tunable to compensate for frequency drift

• Secondary Oscillator using Timer1 @ 32 kHz

• Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops

2.5 PLL Frequency Multiplier

A Phase Locked Loop (PLL) circuit is provided as an

option for users who wish to use a lower frequency

oscillator circuit or to clock the device up to its highest

rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator

2.5.1 HSPLL OSCILLATOR MODE

The HSPLL mode makes use of the HS Oscillator mode for

frequencies up to 10 MHz. A PLL then multiplies the

oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode. The PLL is only available to the crystal oscillator when the FOSC<3:0> Configuration bits are programmed for HSPLL mode (= 0110).

FIGURE 2-8: PIC18F2420/2520/4420/4520 CLOCK DIAGRAM