Functional Block Diagrams

   DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM.

Features

• VDD = VDDQ = +1.5V ±0.075V

• 1.5V center-terminated push/pull I/O

• Differential bidirectional data strobe

• 8n-bit prefetch architecture

• Differential clock inputs (CK, CK#)

• 8 internal banks

• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals

• CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11

• POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2

• CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on t CK

• Fixed burst leCM GROUPh (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])

• Selectable BC4 or BL8 on-the-fly (OTF)

• Self refresh mode

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