74HC4052; 74HCT4052

Dual 4-channel analog multiplexer, demultiplexer

FEATURES

• Wide analog input voltage range from −5 V to +5 V

• Low ON-resistance:

  – 80 Ω (typical) at V_CC − V_EE = 4.5 V

  – 70 Ω (typical) at V_CC − V_EE = 6.0 V

  – 60 Ω (typical) at V_CC − V_EE = 9.0 V

• Logic level translation: to enable 5 V logic to communicate with ±5 V analog signals

• Typical “break before make” built in

• Complies with JEDEC standard no. 7A

• ESD protection:

  – HBM EIA/JESD22-A114-B exceeds 2000 V

  – MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 °C to +85 °C and −40 °C to +125 °C.

APPLICATIONS

• Analog multiplexing and demultiplexing

• Digital multiplexing and demultiplexing

• Signal gating.

DESCRIPTION

The 74HC4052 and 74HCT4052 are high-speed Si-gate CMOS devices and are pin compatible with the HEF4052B. They are specified in compliance with JEDEC standard no. 7A.

The 74HC4052 and 74HCT4052 are dual 4-channel analog multiplexers or demultiplexers with common select logic. Each multiplexer has four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ). The common channel select logics include two digital select inputs (pins S0 and S1) and an active LOW enable input (pin E). When pin E = LOW, one of the four switches is selected (low-impedance ON-state) with pins S0 and S1. When pin E = HIGH, all switches are in the high-impedance OFF-state, independent of pins S0 and S1.

V_CC and GND are the supply voltage pins for the digital control inputs (pins S0, S1, and E). The V_CC to GND ranges are 2.0 V to 10.0 V for 74HC4052 and 4.5 V to 5.5 V for 74HCT4052. The analog inputs/outputs (pins nY0 to nY3 and nZ) can swing between V_CC as a positive limit and V_EE as a negative limit. V_CC − V_EE may not exceed 10.0 V.

For operation as a digital multiplexer/demultiplexer, V_EE is connected to GND (typically ground).

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to V_EE = GND (ground = 0 V); note 1.

Notes

1. To avoid drawing V_CC current out of pins nZ, when switch current flows in pins nYn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pins nZ, no V_CC current will flow out of pins nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at pins nYn and nZ may not exceed V_CC or V_EE.

2. For DIP16 packages: above 70 °C derate linearly with 12 mW/K.

    For SO16 packages: above 70 °C derate linearly with 8 mW/K.

    For SSOP16 and TSSOP16 packages: above 60 °C derate linearly with 5.5 mW/K.

    For DHVQFN16 packages: above 60 °C derate linearly with 4.5 mW/K.

Functional diagram