Custom Multilayer HDI Interconnect PCB Circuit Board 0.4mm Half Plating Vias
10 Layer Multilayer HDI Circuit Board 0.4mm Half Plating Vias PCB
♦ What is Blind Hole in PCBs?
Half Plating Vias (also called Partial Plating Vias or Non-Through Plating Vias) are a type of via structure used in printed circuit board (PCB) design where the conductive plating does not fully extend through the entire via hole.
Key Characteristics:
-
-
Partial Copper Plating:
- Unlike standard fully plated through-hole vias, half-plated vias have copper plating only on one side or a portion of the via wall, leaving the other side unplated or partially plated.
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Controlled Depth Plating:
- The plating may stop at a certain depth, either by laser drilling, controlled electroplating, or plugging material (e.g., resin).
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Common Applications:
- Blind/Buried Vias: Used in HDI (High-Density Interconnect) PCBs to connect inner layers without passing through the entire board.
- Via-in-Pad Designs: Helps prevent solder wicking into the via during assembly.
- RF/Microwave PCBs: Reduces parasitic capacitance and improves signal integrity.
- Thermal Management: Used in thermal vias to control heat dissipation.
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Manufacturing Methods:
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- Laser Drilling + Plating: Laser creates a cavity, followed by selective plating.
- Plugging & Partial Plating: Filling part of the via with dielectric material before plating.
- Sequential Lamination: Used in HDI PCBs to create buried or blind half-plated vias.
♦ Comparison with Other Via Types?
| Via Type | Plating Coverage | Usage |
|---|---|---|
| Through-Hole Via | Fully plated (entire hole) | Standard PCBs |
| Blind Via | Plated from surface to inner layer | HDI PCBs |
| Buried Via | Plated between inner layers | Multilayer PCBs |
| Half Plating Via | Partially plated (one side or depth-controlled) | Specialized designs |
♦ Conclusion
Half plating vias are an advanced PCB design technique used to optimize space, signal performance, and manufacturability in complex multilayer boards, especially in high-frequency and miniaturized electronics.
♦ Technical Parameters
|
Item |
Spec |
|
Layers |
1~64 |
|
Board Thickness |
0.1mm-10 mm |
|
Material |
FR-4, CEM-1/CEM-3, PI, High Tg, Rogers, PTEF, Alu/Cu Base,Ceramic, etc |
|
Max Panel Size |
800mm×1200mm |
|
Min Hole Size |
0.075mm |
|
Min Line Width/Space |
Standard: 3mil(0.075mm) Advance: 2mil |
|
Board Outline Tolerance |
士0.10mm |
|
Insulation Layer Thickness |
0.075mm--5.00mm |
|
Out Layer Copper Thickness |
18um--350um |
|
Drilling Hole (Mechanical) |
17um--175um |
|
Finish Hole (Mechanical) |
17um--175um |
|
Diameter Tolerance (Mechanical) |
0.05mm |
|
Registration (Mechanical) |
0.075mm |
|
Aspect Ratio |
17:01 |
|
Solder Mask Type |
LPI |
|
SMT Min. Solder Mask Width |
0.075mm |
|
Min. Solder Mask Clearance |
0.05mm |
|
Plug Hole Diameter |
0.25mm--0.60mm |
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