FBGA-200 DRAM Memory Chip 8Gb X16 X2 Channel LPDDR4X IS43LQ32256B-062BLI

Dynamic Random Access Memory DRAM 8Gb x16 x2 channel Mobile LPDDR4/LPDDR4X IS43LQ32256B-062BLI

• Configuration: 256Mb x16 x 2 channels - 8 internal banks per channel
• Low-voltage Core and I/O Power Supplies:
  • VDD1 = 1.70-1.95V
  • VDD2 = 1.06-1.17V
  • VDDQ = 1.06-1.17V (LPDDR4)
  • VDDQ = 0.57-0.65V (LPDDR4X)
• LVSTL (Low Voltage Swing Terminated Logic) I/O Interface
• Internal VREF and VREF Training
• Dynamic ODT: DQ ODT: VSSQ Termination, CA ODT: VSS Termination
• Max. Clock Frequency: 1866MHz (3733Mbps)
• 16n Pre-fetch DDR architecture
• Single data rate (multiple cycles) command/address bus
• Bidirectional/differential data strobe per byte of data (DQS/DQS#)
• Programmable and on-the-fly burst lengths (BL=16, 32)
• ZQ Calibration
• Operation Temperature Ranges:
  • Industrial (TC = -40°C to 95°C)
  • Automotive, A1 (TC = -40°C to 95°C)
  • Automotive, A2 (TC = -40°C to 105°C)
  • Automotive, A3 (TC = -40°C to 125°C)
• Clock-Stop capability
• On-chip temperature sensor whose status can be read from MR4
• 200-ball x32 BGA Package (10x14.5 mm)

The IS43/46LQ32256B and IS43/46LQ32256BL are 8Gbit CMOS LPDDR4 SDRAM. The device is organized as 2 channels per device, and each channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins.

This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth.

According to the standard export packaging. Customers can choose from cartons, wooden cases and wooden pallets according to their own requirements.