This device utilizes a multistage differential pipeline architecture with on-chip error correction logic to ensure 14-bit accuracy and no missing codes across the full industrial temperature range.

• Resolution & Sampling Rate: 14-bit resolution, 40 MSPS maximum sampling rate
• Architecture: Multistage differential pipeline with output error correction logic
• Analog Input: Differential input with 700 MHz bandwidth; 2 V p-p full-scale input range
• On-Chip Integration: Integrated high-performance sample-and-hold (S/H) circuit and voltage reference
• Linearity: Typical DNL = ±0.25 LSB; guaranteed no missing codes

• SNR: 74.7 dBFS (typical at fIN = 9.7 MHz)
• SFDR: 95 dBc (typical at fIN = 9.7 MHz)
• Power Consumption: Low power operation, ~65 mW at 40 MSPS

• Differential Clock Input: Accepts external differential clock; supports 1×, 2×, or 4× clock division ratios
• Programmable Alignment: Flexible clock and data alignment via SPI for system timing optimization

• Output Formats: Supports offset binary, Gray code, or twos complement data formats
• SPI Control: Full programmability via 3-wire serial port interface (SPI)
• Test Pattern Generation: Built-in deterministic, pseudorandom, and user-defined digital test patterns
• Power Modes: Energy-saving power-down modes (standby and shutdown)

• Package: 32-lead LFCSP (5×5 mm), RoHS-compliant
• Temperature Range: Industrial grade: −40°C to +85°C
• Power Supplies: AVDD = 1.8 V (analog); DRVDD = 1.8 V to 3.3 V (digital output)

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