3008 Invensys TRICONEX Main Processors

Product Details:

Description:

Model 3008 Main Processors are available for Tricon v9.6 and later systems.
For detailed specifications, see the
Planning and Installation Guide for
Tricon Systems.
Three MPs must be installed in the
main chassis of every Tricon system.
Each MP independently communicates
with its I/O subsystem and executes the
user-written control program.
Sequence of Events (SOE)
and Time Synchronization
During each scan, the MPs inspect
designated discrete variables for state
changes known as events. When an
event occurs, the MPs save the current
variable state and time stamp in the
buffer of an SOE block.
If multiple Tricon systems are
connected by means of NCMs, the time
synchronization capability ensures a
consistent time base for effective SOE
time-stamping.
Diagnostics
Extensive diagnostics validate the
health of each MP, I/O module and
communication channel. Transient
faults are recorded and masked by the
hardware majority-voting circuit.
Persistent faults are diagnosed and the
errant module is hot-replaced.
MP diagnostics perform these tasks:
• Verify fixed-program memory and
static RAM
• Test all basic processor and floatingpoint instructions and operating
modes
• Validate user memory by means of
the TriBus hardware-voting circuitry
• Verify the shared memory interface
with each I/O communication
processor and channel
• Verify handshake and interrupt
signals between the CPU, each I/O
communication processor and
channel
• Check each I/O communication
processor and channel
microprocessor, ROM, shared
memory access and loopback of RS485 transceivers
• Verify the TriClock and TriBus
interfaces