It  contains a two-dimensional row- and column-based architecture to implement custom logic. Row and column interconnects provide signal interconnects between the logic array blocks (LABs). The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. The MultiTrack interconnect provides fast granular timing delays between LABs. The fast routing between LEs provides minimum timing delay for added levels of logic versus globally routed interconnect structures. The MAX II device I/O pins are fed by I/O elements (IOE) located at the ends of LAB rows and columns around the periphery of the device. Each IOE contains a bidirectional I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs and various single-ended standards, such as 66-MHz, 32-bit PCI, and LVTTL. MAX II devices provide a global clock network. The global clock network consists of four global clock lines that drive throughout the entire device, providing clocks for all resources within the device. The global clock lines can also be used for control signals such as clear, preset, or output enable.

Product name:EPM240GT100C3N
Manufacturer: Intel	Product Category: CPLD - Complex Programmable Logic Device
Number of large batteries: 192	Number of logical array blocks - LAB: 24
Maximum operating frequency: 304 MHz	Propagation Delay—Max: 4.7 ns
Number of inputs/outputs: 80 I/O	Operating supply voltage: 1.8 V
Minimum operating temperature: 0 C	Maximum operating temperature: + 70 C
Installation style: SMD/SMT	Package/Case: TQFP-100
Number of logic elements: 240	Operating supply current: 40 mA
Product Type: CPLD - Complex Programmable Logic Devices	Series: EPM240
Factory Packing Quantity: 90	Subcategory: Programmable Logic ICs
Supply Voltage - Maximum: 1.89 V	Supply Voltage - Min: 1.71 V
Total memory: 8192 bit	Unit weight: 600 mg