ADSP-21060LCW-160

SUMMARY

High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features 240-lead thermally enhanced MQFP_PQ4 package, 225-ball plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages KEY FEATURES—PROCESSOR CORE 40 MIPS, 25 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Dual data address generators with modulo and bit-reverse addressing) Efficient program sequencing with zero-overhead looping: Single-cycle loop setup IEEE JTAG Standard 1149.1 Test Access Port and on-chip emulation 32-bit single-precision and 40-bit extended-precision IEEE floating-point data formats or 32-bit fixed-point data format

PARALLEL COMPUTATIONS

Single-cycle multiply and ALU operations in parallel with dual memory read/writes and instruction fetch Multiply with add and subtract for accelerated FFT butterfly computation UP TO 4M BIT ON-CHIP SRAM Dual-ported for independent access by core processor and DMA OFF-CHIP MEMORY INTERFACING 4 gigawords addressable Programmable wait state generation, page-mode DRAM support

Product parameters

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