Features

• 15,600 to 179,400 equivalent LEs; see Table 1–1

• New and innovative adaptive logic module (ALM), the basic

  building block of the Stratix II architecture, maximizes performance

  and resource usage efficiency

• Up to 9,383,040 RAM bits (1,172,880 bytes) available without

  reducing logic resources

• TriMatrix memory consisting of three RAM block sizes to implement

  true dual-port memory and first-in first-out (FIFO) buffers

• High-speed DSP blocks provide dedicated implementation of

  multipliers (at up to 450 MHz), multiply-accumulate functions, and

  finite impulse response (FIR) filters

• Up to 16 global clocks with 24 clocking resources per device region

• Clock control blocks support dynamic clock network enable/disable,

  which allows clock networks to power down to reduce power

  consumption in user mode

• Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device

  provide spread spectrum, programmable bandwidth, clock switch- over, real-time PLL reconfiguration, and advanced multiplication and phase shifting

• Support for numerous single-ended and differential I/O standards

• High-speed differential I/O support with DPA circuitry for 1-Gbps

  performance

• Support for high-speed networking and communications bus

  standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY

  Level 4), HyperTransportTM technology, and SFI-4

• Support for high-speed external memory, including DDR and DDR2

  SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM

• Support for multiple intellectual property megafunctions from

  Altera MegaCore® functions and Altera Megafunction Partners

  Program (AMPPSM) megafunctions

• Support for design security using configuration bitstream

  encryption

• Support for remote configuration updates