EP3C40F324C8N EP3C40F484C8 EP3C40F484C8N EP3C40F484I7N EP3C40F780C6N EP3C40Q240C8N Programmable Logic ICS Field Program

Lowest Power FPGAs

• Lowest power consumption with TSMC low-power process technology and Altera® power-aware design flow

Design Security Feature

Cyclone III LS devices offer the following design security features:

• Configuration security using advanced encryption standard (AES) with 256-bit volatile key

• Routing architecture optimized for design separation flow with the Quartus® II software

■ Design separation flow achieves both physical and functional isolation between design partitions

• Ability to disable external JTAG port

• Error Detection (ED) Cycle Indicator to core

  • Provides a pass or fail indicator at every ED cycle

  • Provides visibility over intentional or unintentional change of configuration

    random access memory (CRAM) bits

• Ability to perform zeroization to clear contents of the FPGA logic, CRAM, embedded memory, and AES key

• Internal oscillator enables system monitor and health check capabilities

  Increased System Integration

  • High memory-to-logic and multiplier-to-logic ratio

  • High I/O count, low-and mid-range density devices for user I/O constrained

    applications

    • Adjustable I/O slew rates to improve signal integrity

    • Supports I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL, bus LVDS (BLVDS), LVDS, mini-LVDS, RSDS, and PPDS

    • Supports the multi-value on-chip termination (OCT) calibration feature to eliminate variations over process, voltage, and temperature (PVT)

  • Four phase-locked loops (PLLs) per device provide robust clock management and synthesis for device clock management, external system clock management, and I/O interfaces

    • Five outputs per PLL

    • Cascadable to save I/Os, ease PCB routing, and reduce jitter

    • Dynamically reconfigurable to change phase shift, frequency multiplication or division, or both, and input frequency in the system without reconfiguring the device

  • Remote system upgrade without the aid of an external controller

  • Dedicated cyclical redundancy code checker circuitry to detect single-event upset

    (SEU) issues

  • Nios® II embedded processor for Cyclone III device family, offering low cost and custom-fit embedded processing solutions