CY7C1328G-133AXI electronic ic chip Integrated Circuit Chip 4-Mbit (256K x 18) Pipelined DCD Sync SRAM

CY7C1328G 4-Mbit (256K x 18) Pipelined DCD Sync SRAM

Features

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

  — Depth expansion without wait state

• 256K × 18 common I/O architecture

• 3.3V core power supply (VDD)

• 3.3V/2.5V I/O power supply (VDDQ)

• Fast clock-to-output times

  — 2.6 ns (for 250-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• Available in lead-free 100-Pin TQFP package

• “ZZ” Sleep Mode option

Functional Description

The CY7C1328G SRAM integrates 256K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance.

The CY7C1328G operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................................... –65°C to +150°C

Ambient Temperature with Power Applied.......................–55°C to +125°C

Supply Voltage on V_DD Relative to GND........................... –0.5V to +4.6V

Supply Voltage on V_DDQ Relative to GND ........................  –0.5V to +V_DD

DC Voltage Applied to Outputs in tri-sta.................. –0.5V to V_DDQ + 0.5V

DC Input Voltage ....................................................... –0.5V to V_DD + 0.5V

Current into Outputs (LOW)............................................................. 20 mA

Static Discharge Voltage............................................................... > 2001V

(per MIL-STD-883,Method 3015)

Latch -up Current ........................................................................ > 200 mA

Functional Block Diagram

Package Diagram

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