NVT2008PW Translation - Voltage Levels +/-50mA 1.5ns 1-5.5V Integrated Circuits ICs
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MOQ:
1PCS
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Brand:
N-X-P
Product Description
NVT2008PW Translation - Voltage Levels +/-50mA 1.5ns 1-5.5V
| Product Attribute | Attribute Value |
|---|---|
| N-X-P | |
| Product Category: | Translation - Voltage Levels |
| RoHS: | Details |
| NVT2008 | |
| GTL to LVTTL | |
| SMD/SMT | |
| TSSOP-20 | |
| 1 V | |
| 5.5 V | |
| - 40 C | |
| + 85 C | |
| 1.5 ns | |
| Reel | |
| Cut Tape | |
| MouseReel | |
| Brand: | N-X-P Semiconductors |
| High Level Output Current: | 50 mA |
| Logic Type: | Bidirectional Voltage Level Translator |
| Low Level Output Current: | - 50 mA |
| Product Type: | Translation - Voltage Levels |
| 2500 | |
| Subcategory: | Logic ICs |
| Part # Aliases: | 935292076118 |
| Unit Weight: | 0.004068 oz |
General description
The NVT2008/NVT2010 are bidirectional voltage level translators operational from 1.0 V
to 3.6 V (Vre(A) and 1.8 V to 5.5 V (ere(B), which allow bidirectional voltage translations
between 1.0 V and 5 V without the need for a direction pin in open-drain or push-pull
applications. Bit widths of 8-bit to 10-bit are offered for level translation application with
transmission speeds < 33 MHz for an open-drain system with a 50 pF capacitance and a
pul-up of 197 2.
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of the
switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to the
drain pul-up supply voltage (Vpu(D) by the pull-up resistors. This functionality allows a
seamless translation between higher and lower voltages selected by the user without the
need for directional control.
When EN is HIGH, the translator switch is on, and the An /0 are connected to the Bn /O,
respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Ve(B)- To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
Features and benefits
Provides bidirectional voltage translation with no direction pin
■Less than 1.5 ns maximum propagation delay
■Allows voltage level translation between:
◆1.0Vet(A) and 1.8V, 2.5V, 3.3V or 5V Vrl(B)
◆1.2Vel(A) and 1.8V, 2.5V, 3.3V or 5V Vrl(B)
◆1.8V VrelA) and 3.3V or 5 V Vre(B)
◆2.5V VretA) and 5V Ve(B)
◆3.3 V VrlA) and 5 V Vret(B)
■Low 3.5 0 ON-state connection between input and output ports provides less signal distortion
■5 V tolerant /O ports to support mixed-mode signal operation
■High-impedance An and Bn pins for EN = LOW
■Lock-up free operation
■Flow through pinout for ease of printed-circuit board trace routing
■ESD protection exceeds 4 kV HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
■Packages offered: TSSOP20, DHVQFN20, TSSOP24, DHVQFN24 HVQFN24
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Company
Wisdtech Technology Co.,Limited
Location
Room 1205-1207, Nanguang building, Huafu Road, Futian District, Shenzhen, Guangdong, China
Contact Person
Tao