MPC9443AER2 Clock Buffer FSL 1-16 LVCMOS Fanout Buffer Integrated Circuits ICs
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Product Description
MPC9443AER2 Clock Buffer FSL 1-16 LVCMOS Fanout Buffer Integrated Circuits ICs
| IDT | |
| Product Category: | Clock Buffer |
| RoHS: | Details |
| Brand: | Renesas Electronics |
| Moisture Sensitive: | Yes |
| Packaging: | Reel |
| Packaging: | Cut Tape |
| Product Type: | Clock Buffers |
| Subcategory: | Clock & Timer ICs |
Description:
The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are
generated and retimed on-chip to ensure minimal skew between the four output banks.
Two independent LVPECL compatible clock inputs are availble. This feature supports redundant
dffrential clock sources. In aitin, the MPC9443 supports single ended LVCMOS clock distribution
systems. Each of the four output banks can be individually supplied by 2.5 V or 3.3 V, supporting
mixed voltage applications. The FSELx pins choose between division of the input reference
frequency by one or two. The frequency divider can be set individually for each output bank.
The MPC9443 output banks are in high-impedance state by deasserting the OEN pins. Asserting
OEN will the enable output banks. Please see Table 4. Output High-lmpedance Control (OEN) for
details. The outputs can be synchronously stopped (logic low state). The outputs provide LVCMOS
compatible levels with the capability to drive terminated 50 Q transmission lines. For series
terminated transmission lines, each of the MPC9443 outputs can drive one or two traces giving
the devices an effective fanout of 1:32 at Vcc = 3.3 V. The device is packaged in a 7x7 mm2 48-lead
LQFP package.
The Freescale Semiconductor, Inc. MPC9443 is a 2.5 V and 3.3 V compatible 1:16
dlock distribution buffer designed for low-voltage high-performance telecom, networking
and computing aplications. The device supports 3.3 V, 2.5 V and dual supply voltage
(mixed-voltage) applications. The MPC9443 offers 16 low-skew outputs which are divided
into 4 individually configurable banks. Each output bank can be individually supplied by
2.5 V or 3.3 V, individually set to run at 1X or 1/2X of the input clock frequency or be
disabled (logic low output state). Two selectable LVPECL compatible inputs support
differential clock distribution systems. In addition, one selectable LVCMOS input is
provided for LVCMOS clock distribution systems. The MPC9443 is specified for the
extended temperature range of - 40 to +85*C.
Features
●Configurable 16 outputs LVCMOS clock distribution buffer
●Compatible to single, dual and mixed 3.3 V1 2.5 V voltage supply
●Output clock frequency up to 350 MHz
●Designed for high-performance telecom, networking and computer applications
●Supports aplications requiring clock redundancy
●Maximum output skew of 250 ps (125 ps within one bank)
●Selectable output configurations per output bank
●Individually per- bank high-impedance tristate
●Output disable (stop in logic low state) control
●48-lead LQFP package, Pb-free
●Ambient operating temperature range of -40 to 85°C
●For functional replacement part use 87016i
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