Beijing Silk Road Enterprise Management Services Co., Ltd.
                                                                                                           
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Dual output MEMS clock generator MICROCHIP DSC612RI1A-012M with frequency range from 2 kHz to 100 MHz

Price Negotiable
Price: Negotiable
MOQ: Negotiable
Delivery Time: Negotiable
Product Description

Product Overview

The DSC612 is a MEMS low power, ultra-small footprint, crystal-less family of clock generators. It eliminates the need for an external crystal or reference clock, offering enhanced reliability and accelerated product development. The DSC612 generates up to two independent LVCMOS output clocks, each configurable from 2 kHz to 100 MHz. It features Microchips PureSilicon MEMS technology for low jitter and high stability across a wide range of supply voltages and temperatures. The device includes control inputs for output enable/disable, standby, sleep, spread spectrum enable, and frequency select. Available in space-saving VFLGA packages, it is ideal for low power, portable, consumer, and industrial applications.

Product Attributes

  • Brand: Microchip Technology Inc.
  • Certifications: AEC-Q100 Available (Automotive Option), MIL-STD-883E Method 2002.3 (Shock), MIL-STD-883E Method 2007.2 (Vibration), Lead-Free, RoHS-Compliant

Technical Specifications

ParameterSymbolMin.Typ.Max.UnitsConditions
Supply VoltageVDD1.713.63VNote 1
Active Supply CurrentIDD56mAfCLK1 = 27 MHz, fCLK2 = 25 MHz, VDD = 1.8V, No Load
Active Supply Current (Sleep Mode, 1 PLL Off)IDDSL3mACLK2 = SLEEP, fCLK1 = 25 MHz, VDD = 1.8V, No Load
Active Supply Current (32.768 kHz Output Only)IDD32k1.4mACLK2 = SLEEP, fCLK1 = 32.768 kHz, VDD = 1.8V, No Load
Standby Supply CurrentISTDBY1.0AVDD = 1.8V/2.5V
Standby Supply CurrentISTDBY1.5AVDD = 3.3V
Frequency Stabilityf20ppmAll temperature ranges
Frequency Stabilityf25ppm
Frequency Stabilityf50ppm
Agingf5ppm1st year @ +25C
Agingf1ppmPer year after the first year
Startup TimetSU1.5msFrom 90% VDD to valid clock output, T = +25C
Input Logic HighVIH0.7 x VDDV
Input Logic LowVIL0.3 x VDDV
Output Disable TimetDA200 + 2 PeriodsnsNote 5
Output Enable TimetEN1.0sNote 6
Output Logic HighVOHY0.8 x VDDVI = 6 mA (high drive) or I = 3 mA (standard drive)
Output Logic LowVOLY0.2 x VDDI = 6 mA (high drive) or I = 3 mA (standard drive)
Output Transition Time, Rise Time/Fall Time (Standard Drive)tRY1/tFY11.22.0nsCL = 10 pF, VDD = 1.8V
Output Transition Time, Rise Time/Fall Time (Standard Drive)tRY1/tFY10.61.2nsCL = 10 pF, VDD = 2.5V/3.3V
Output Transition Time, Rise Time/Fall Time (High Drive)tRY2/tFY21.01.5nsCL = 15 pF, VDD = 1.8V
Output Transition Time, Rise Time/Fall Time (High Drive)tRY2/tFY20.51.0nsCL = 15 pF, VDD = 2.5V/3.3V
Frequencyf00.002100MHz
Output Duty CycleSYM4555%
Period Jitter, RMSJPER17psfCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 1.8V
Period Jitter, RMSJPER14psfCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 3.3V
Period Jitter, RMSJPER9psfCLK1 = 27 MHz, fCLK2 = 27 MHz or 32.768 kHz, VDD = 3.3V
Period Jitter, Peak-to-PeakJPER120psfCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 1.8V
Period Jitter, Peak-to-PeakJPER100psfCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 3.3V
Period Jitter, Peak-to-PeakJPER80psfCLK1 = 27 MHz, fCLK2 = 27 MHz or 32.768 kHz, VDD = 3.3V
Cycle-to-Cycle Jitter (peak)JCy-Cy105psfCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 1.8V
Cycle-to-Cycle Jitter (peak)JCy-Cy90psfCLK1 = 24 MHz, fCLK2 = 27 MHz, VDD = 3.3V
Cycle-to-Cycle Jitter (peak)JCy-Cy70psfCLK1 = 27 MHz, fCLK2 = 27 MHz or 32.768 kHz, VDD = 3.3V
Junction Operating TemperatureTJ+150C
Storage Temperature RangeTS55+150C

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Company Beijing Silk Road Enterprise Management Services Co., Ltd.
Location 16 Floor, Unit B, Jiatai International Mansion, No 41, Dongsihuan Zhong Road, Chaoyang District, Beijing
Contact Person Sellina

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