AEC Q200 Compliant CTS CA70P10003HLR Clock Oscillator with Extended Temperature Range and LVPECL LVDS

Price Negotiable

Price: Negotiable

MOQ: Negotiable

Delivery Time: Negotiable

Product Description

Product Overview

The CTS Model CA70P/L is a cost-effective, compact Clock Oscillator (XO) designed for automotive electronics operating in extended temperature ranges. It features optional LVPECL or LVDS compatible outputs, offering excellent stability and low jitter/phase noise performance. This product is AEC-Q200 compliant.

Product Attributes

Brand: CTS
Model: CA70P/L
Certifications: AEC-Q200 Compliant
Package: Ceramic Surface Mount
Packaging: Tape and Reel (EIA-481)
Origin: USA (implied by www.ctscorp.com)

Technical Specifications

Model	Output Type	Frequency Range (MHz)	Supply Voltage (Vdc)	Frequency Stability (ppm)	Operating Temperature Range (C)	Package Size (mm)
CA70P/L	LVPECL or LVDS	13.5 160	+2.5V or +3.3V (+1.8V LVDS only)	25, 30, 50, 100, 150	-40 to +85, -40 to +105, -40 to +125	7.0 x 5.0 x 1.6

Parameter	Symbol	Conditions	Min	Typ	Max	Unit
Maximum Supply Voltage	VCC		-0.5		5.0	V
Supply Current (LVPECL)		VCC = +2.5V or +3.3V @ Maximum Load		55	80	mA
Supply Current (LVDS)		VCC = +2.5V or +3.3V @ Maximum Load		45	60	mA
Supply Current (LVDS)		VCC = +1.8V @ Maximum Load		7	20	mA
Storage Temperature	TSTG		-55		+125	C
Frequency Stability [Note 2]	f/fO				150	ppm
Aging (First Year @ +25C, nominal VCC)	f/f25		-3		3	ppm
Output Load (LVPECL)	RL	Terminated to VCC - 2.0V		50		Ohms
Output High Voltage (LVPECL)	VOH	@ VCC - 1.3V	VCC - 1.025		VCC - 0.880	V
Output Low Voltage (LVPECL)	VOL	@ VCC - 1.3V	VCC - 1.810		VCC - 1.620	V
Output Duty Cycle (LVPECL)	SYM		45		55	%
Rise and Fall Time (LVPECL)	TR, TF	@ 20%/80% Levels, RL = 50 Ohms		0.3	0.7	ns
Output Load (LVDS)	RL	Between Outputs		100		Ohms
Output High Voltage (LVDS)	VOH	LVDS Load	1.43	1.60		V
Output Low Voltage (LVDS)	VOL	LVDS Load		0.90	1.10	V
Differential Output Voltage (LVDS)	VOD	RL = 100 Ohms	247	330	454	mV
Offset Voltage (LVDS)	VOS	LVDS Load	1.125	1.25	1.375	V
Output Duty Cycle (LVDS)	SYM		45		55	%
Rise and Fall Time (LVDS)	TR, TF	@ 20%/80% Levels, RL = 100 Ohms		0.4	0.7	ns
Start Up Time	TS	Application of VCC		2	10	ms
Enable Input Voltage	VIH	Pin 1 or 2 Logic '1', Output Enabled	0.7VCC			V
Disable Input Voltage	VIL	Pin 1 or 2 Logic '0', Output Disabled			0.3VCC	V
Disable Time	TPLZ	Pin 1 or 2 Logic '0', Output Disabled			200	ns
Standby Current	IST	Pin 1 Logic '0', Output Disabled			15	A
Enable Time	TPLZ	Pin 1 or 2 Logic '1', Output Enabled			10	ms
Phase Jitter, RMS (40-160MHz)	tjrms	Bandwidth 12kHz to 20MHz		300	500	fs
Phase Jitter, RMS (10-39.999MHz)	tjrms	Bandwidth 12kHz to 5MHz		500		ps