CMOS Oscillator MICROCHIP DSC1001DI1-024.0000 Silicon MEMS Technology for High Reliability Industrial

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Product Description

Product Overview

The DSC1001/3/4 is a silicon MEMS-based CMOS oscillator family offering excellent jitter and stability over a wide range of supply voltages and temperatures. Its crystal-less design provides high reliability, making it suitable for rugged, industrial, and portable applications. Available in industry-standard packages, it serves as a pin-for-pin "drop-in" replacement for standard crystal oscillators, offering longer battery life and reduced power consumption.

Product Attributes

Brand: Microchip Technology Inc.
Certifications: Pb Free, RoHS, Reach SVHC Compliant, AEC-Q100 Reliability Qualified
Material: Silicon MEMS

Technical Specifications

Parameter	Symbol	Min.	Typ.	Max.	Units	Conditions
General Specifications
Frequency Range	F0	1		150	MHz	Single Frequency
Frequency Tolerance	Δf			±10	ppm	Includes frequency variations due to initial tolerance, temperature and power supply voltage
Frequency Tolerance	Δf			±20	ppm	Includes frequency variations due to initial tolerance, temperature and power supply voltage
Frequency Tolerance	Δf			±25	ppm	Includes frequency variations due to initial tolerance, temperature and power supply voltage
Frequency Tolerance	Δf			±50	ppm	Includes frequency variations due to initial tolerance, temperature and power supply voltage
Aging	Δf			±5	ppm	1 year @ +25°C
Standby Supply Current	I_DD			15	µA	T = +25°C
Output Startup Time	t_SU		1.0	1.3	ms	T = +25°C, Note 1
Output Disable Time	t_DA		20	100	ns
Output Duty Cycle	SYM	45		55	%
Input Logic Level High	V_IH	0.75 x V_DD			V
Input Logic Level Low	V_IL			0.25 x V_DD	V
Output Transition Rise Time (DSC1001)	t_R		1.4	3.0	ns	CL = 15 pF, T = +25°C, 20% to 80%
Output Transition Fall Time (DSC1001)	t_F		1.0	3.0	ns	CL = 15 pF, T = +25°C, 20% to 80%
Max. Cycle-to-Cycle Jitter	J_CC		60		ps	f = 100 MHz (Note 2)
Period Jitter	J_P		10	15	ps_RMS	f = 100 MHz (Note 2)
Operating Conditions
Supply Voltage	V_DD	+1.7		+3.6	V
Output Load	Z_L	R > 10 kΩ, C ≤ 15 pF
Temperature Specifications
Operating Temperature Range	T_A	–40		+105	°C	Ordering Option L
Operating Temperature Range	T_A	–40		+85	°C	Ordering Option I
Operating Temperature Range	T_A	–20		+70	°C	Ordering Option E
Junction Operating Temperature	T_J			+150	°C
Storage Temperature Range	T_A	–55		+150	°C
Soldering Temperature Range	T_S			+260	°C	40 sec. max
Supply Current (VDD = 1.8V, TA = +25°C)
Supply Current, No Load (1 MHz)	I_DD		6.0	6.3	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (27 MHz)	I_DD		6.5	7.1	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (70 MHz)	I_DD		7.2	8.5	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (150 MHz)	I_DD		8.3	11.9	mA	CL = 0 pF, RL = ∞
Output Logic Levels (VDD = 1.8V, TA = +25°C)
Output Logic Level High (DSC1001)	V_OH	0.8 x V_DD			V	–4 mA, CL = 15 pF
Output Logic Level Low (DSC1001)	V_OL			0.2 x V_DD	V	4 mA, CL = 15 pF
Supply Current (VDD = 2.5V, TA = +25°C)
Supply Current, No Load (1 MHz)	I_DD		6.0	6.4	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (27 MHz)	I_DD		6.7	7.5	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (70 MHz)	I_DD		7.7	9.4	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (150 MHz)	I_DD		9.6	13.9	mA	CL = 0 pF, RL = ∞
Output Logic Levels (VDD = 2.5V, TA = +25°C)
Output Logic Level High (DSC1001)	V_OH	0.8 x V_DD			V	–4 mA, CL = 15 pF
Output Logic Level Low (DSC1001)	V_OL			0.2 x V_DD	V	4 mA, CL = 15 pF
Supply Current (VDD = 3.3V, TA = +25°C)
Supply Current, No Load (1 MHz)	I_DD		6.0	6.5	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (27 MHz)	I_DD		6.8	8.0	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (70 MHz)	I_DD		8.2	10.5	mA	CL = 0 pF, RL = ∞
Supply Current, No Load (150 MHz)	I_DD		10.8	16.6	mA	CL = 0 pF, RL = ∞
Output Logic Levels (VDD = 3.3V, TA = +25°C)
Output Logic Level High (DSC1001)	V_OH	0.8 x V_DD			V	–4 mA, CL = 15 pF
Output Logic Level Low (DSC1001)	V_OL			0.2 x V_DD	V	4 mA, CL = 15 pF
Jitter (TA = +25°C)
Max. Cycle-to-Cycle Jitter (VDD=2.5V)	J_CC		50		ps	f = 100 MHz (Note 2)
Period Jitter (VDD=2.5V)	J_P		5	10	ps_RMS	f = 100 MHz (Note 2)
Max. Cycle-to-Cycle Jitter (VDD=3.3V)	J_CC		50		ps	f = 100 MHz (Note 2)
Period Jitter (VDD=3.3V)	J_P		5	10	ps_RMS	f = 100 MHz (Note 2)
Notes: 1: t_SU is time to stable output frequency after V_DD is applied. t_SU and t_EN (after EN is asserted) are identical values. 2: Measured over 50k clock cycles.