Ultra Series Crystal Oscillator SKYWORKS 545ACA1000M00BCG with Low Phase Noise and Ultra Low Jitter
Price:
Negotiable
MOQ:
Negotiable
Delivery Time:
Negotiable
Product Description
Skyworks Solutions Si545 Ultra Series Crystal Oscillator
Product Overview
The Skyworks Solutions Si545 Ultra Series Crystal Oscillator is an advanced clock generator utilizing proprietary 4th generation DSPLL technology. It delivers ultra-low jitter and low phase noise across any output frequency from 0.2 to 1500 MHz with
Product Attributes
- Brand: Skyworks Solutions
- Technology: DSPLL
- Series: Ultra Series
Technical Specifications
| Parameter | Symbol | Test Condition/Comment | Min | Typ | Max | Unit |
|---|---|---|---|---|---|---|
| Temperature Range | TA | 40 | 85 | C | ||
| Frequency Range | FCLK | LVPECL, LVDS, CML | 0.2 | 1500 | MHz | |
| Frequency Range | FCLK | HCSL | 0.2 | 400 | MHz | |
| Frequency Range | FCLK | CMOS, Dual CMOS | 0.2 | 250 | MHz | |
| Supply Voltage | VDD | 3.3 V | 3.135 | 3.3 | 3.465 | V |
| Supply Voltage | VDD | 2.5 V | 2.375 | 2.5 | 2.625 | V |
| Supply Voltage | VDD | 1.8 V | 1.71 | 1.8 | 1.89 | V |
| Supply Current | IDD | LVPECL (output enabled) | 107 | 153 | mA | |
| Supply Current | IDD | LVDS/CML (output enabled) | 83 | 121 | mA | |
| Supply Current | IDD | HCSL (output enabled) | 86 | 126 | mA | |
| Supply Current | IDD | HCSL-Fast (output enabled) | 94 | 138 | mA | |
| Supply Current | IDD | CMOS (output enabled) | 87 | 127 | mA | |
| Supply Current | IDD | Dual CMOS (output enabled) | 92 | 141 | mA | |
| Supply Current | IDD | Tristate Hi-Z (output disabled) | 73 | 112 | mA | |
| Temperature Stability | Grade A | 20 | 20 | ppm | ||
| Temperature Stability | Grade B | 10 | 10 | ppm | ||
| Temperature Stability | Grade C | 7 | 7 | ppm | ||
| Total Stability | FSTAB | Grade A | 50 | 50 | ppm | |
| Total Stability | FSTAB | Grade B | 25 | 25 | ppm | |
| Total Stability | FSTAB | Grade C | 20 | 20 | ppm | |
| Rise/Fall Time (20% to 80% VPP) | TR/TF | LVPECL/LVDS/CML | 350 | ps | ||
| Rise/Fall Time (20% to 80% VPP) | TR/TF | CMOS / Dual CMOS, (CL = 5 pF) | 0.5 | 1.5 | ns | |
| Rise/Fall Time (20% to 80% VPP) | TR/TF | HCSL, FCLK >50 MHz | 550 | ps | ||
| Rise/Fall Time (20% to 80% VPP) | TR/TF | HCSL-Fast, FCLK >50 MHz | 275 | ps | ||
| Duty Cycle | DC | All formats | 45 | 55 | % | |
| Output Enable (OE) | VIH | 0.7 VDD | V | |||
| Output Enable (OE) | VIL | 0.3 VDD | V | |||
| Output Disable Time | TD | FCLK > 10 MHz | 3 | s | ||
| Output Enable Time | TE | FCLK > 10 MHz | 20 | s | ||
| Powerup Time | tOSC | Time from 0.9 VDD until output frequency (FCLK) within spec | 10 | ms | ||
| Powerup VDD Ramp Rate | VRAMP | Fastest VDD ramp rate allowed on startup | 100 | V/ms | ||
| Phase Jitter (RMS, 12kHz - 20MHz) | J | 3.2 x 5 mm, All Differential Formats, FCLK 200 MHz | 80 | 110 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) | J | 3.2 x 5 mm, All Differential Formats, 100 MHz FCLK | 100 | 150 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) | J | 5 x 7 mm, All Differential Formats, FCLK 200 MHz | 80 | 130 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) | J | 5 x 7 mm, All Differential Formats, 100 MHz FCLK | 100 | 150 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) | J | 2.5 x 3.2 mm, All Differential Formats, FCLK 200 MHz | 90 | 130 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) | J | 2.5 x 3.2 mm, All Differential Formats, 100 MHz FCLK | 100 | 150 | fs | |
| Phase Jitter (RMS, 12kHz - 20MHz) | J | CMOS / Dual CMOS Formats, 10 MHz FCLK 250 MHz | 200 | fs | ||
| Spurs Induced by External Power Supply Noise | PSNR | LVDS 156.25 MHz Output, 50 mVpp Ripple, 100 kHz sine wave | -83 | dBc | ||
| Spurs Induced by External Power Supply Noise | PSNR | LVDS 156.25 MHz Output, 50 mVpp Ripple, 200 kHz sine wave | -83 | dBc | ||
| Spurs Induced by External Power Supply Noise | PSNR | LVDS 156.25 MHz Output, 50 mVpp Ripple, 500 kHz sine wave | -82 | dBc | ||
| Spurs Induced by External Power Supply Noise | PSNR | LVDS 156.25 MHz Output, 50 mVpp Ripple, 1 MHz sine wave | -85 | dBc | ||
| Package Options | 2.53.2 mm | 3.25 mm | 57 mm | |||
| Total Stability (includes temp, initial accuracy, load pulling, VDD variation, and 20 yr aging at 70 C) | FSTAB | Grade A | -50 | -50 | -50 | ppm |
| Total Stability (includes temp, initial accuracy, load pulling, VDD variation, and 20 yr aging at 70 C) | FSTAB | Grade B | -25 | -25 | -25 | ppm |
| Total Stability (includes temp, initial accuracy, load pulling, VDD variation, and 20 yr aging at 70 C) | FSTAB | Grade C | -20 | -20 | -20 | ppm |
| Output Options | LVPECL, LVDS, CML, HCSL, CMOS, Dual CMOS | |||||
| Environmental Compliance | Mechanical Shock | MIL-STD-883, Method 2002 | ||||
| Environmental Compliance | Mechanical Vibration | MIL-STD-883, Method 2007 | ||||
| Environmental Compliance | Solderability | MIL-STD-883, Method 2003 | ||||
| Environmental Compliance | Gross and Fine Leak | MIL-STD-883, Method 1014 | ||||
| Environmental Compliance | Resistance to Solder Heat | MIL-STD-883, Method 2036 | ||||
| Moisture Sensitivity Level (MSL) | 3.2 x 5, 5 x 7 packages | 1 | ||||
| Moisture Sensitivity Level (MSL) | 2.5 x 3.2 package | 2 | ||||
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Company
Beijing Silk Road Enterprise Management Services Co., Ltd.
Location
16 Floor, Unit B, Jiatai International Mansion, No 41, Dongsihuan Zhong Road, Chaoyang District, Beijing
Contact Person
Sellina