Stable Frequency Oscillator SKYWORKS 510NAA-BBAG with Enhanced Mechanical Robustness and Reliability
Product Overview
The Skyworks Si510/511 Crystal Oscillator (XO) is an advanced, IC-based frequency generation solution utilizing DSPLL technology. It offers any frequency output from 100 kHz to 250 MHz using a single fixed crystal, eliminating the need for multiple crystals for different frequencies. This approach enhances reliability, mechanical robustness, and stability, while providing superior supply noise rejection for low-jitter clock generation in noisy environments. The Si510/511 is factory-configurable for various user specifications and supports industry-standard packages, making it ideal for a wide range of telecommunications, networking, and computing applications.
Product Attributes
- Brand: Skyworks Solutions, Inc.
- Technology: DSPLL
- Certifications: Pb-free, RoHS compliant
- Package Options: 5 x 7 mm, 3.2 x 5 mm, 2.5 x 3.2 mm
- Output Options: Differential (LVPECL, LVDS, HCSL), CMOS, Dual CMOS
- Supply Voltage Options: 3.3 V, 2.5 V, 1.8 V
- Operating Temperature: 40 to 85 C
Technical Specifications
| Parameter | Symbol | Test Condition | Min | Typ | Max | Unit | Si510/511 |
| Supply Voltage | VDD | 3.3 V option | 2.97 | 3.3 | 3.63 | V | ✔ |
| Supply Voltage | VDD | 2.5 V option | 2.25 | 2.5 | 2.75 | V | ✔ |
| Supply Voltage | VDD | 1.8 V option | 1.71 | 1.8 | 1.89 | V | ✔ |
| Supply Current | IDD | CMOS, 100 MHz, single-ended | 21 | 26 | mA | ✔ | |
| Supply Current | IDD | LVDS (output enabled) | 19 | 23 | mA | ✔ | |
| Supply Current | IDD | LVPECL (output enabled) | 39 | 43 | mA | ✔ | |
| Supply Current | IDD | HCSL (output enabled) | 41 | 44 | mA | ✔ | |
| Supply Current | IDD | Tristate (output disabled) | 18 | mA | ✔ | ||
| Nominal Frequency | FO | CMOS, Dual CMOS | 0.1 | 212.5 | MHz | ✔ | |
| Nominal Frequency | FO | LVDS/LVPECL/HCSL | 0.1 | 250 | MHz | ✔ | |
| Total Stability | Grade C | 30 | +30 | ppm | ✔ | ||
| Total Stability | Grade B | 50 | +50 | ppm | ✔ | ||
| Total Stability | Grade A | 100 | +100 | ppm | ✔ | ||
| Startup Time | TSU | Minimum VDD until output frequency (FO) within specification | 10 | ms | ✔ | ||
| Disable Time | TD | FO 10 MHz | 5 | s | ✔ | ||
| Disable Time | TD | FO | 40 | s | ✔ | ||
| Enable Time | TE | FO 10 MHz | 20 | s | ✔ | ||
| Enable Time | TE | FO | 60 | s | ✔ | ||
| CMOS Output Rise/Fall Time | TR/TF | 0.1 to 212.5 MHz, CL = 15 pF | 0.45 | 0.8 | 1.2 | ns | ✔ |
| CMOS Output Rise/Fall Time | TR/TF | 0.1 to 212.5 MHz, CL = no load | 0.3 | 0.6 | 0.9 | ns | ✔ |
| LVPECL Output Rise/Fall Time | TR/TF | 100 | 565 | ps | ✔ | ||
| HCSL Output Rise/Fall Time | TR/TF | 100 | 470 | ps | ✔ | ||
| LVDS Output Rise/Fall Time | TR/TF | 350 | 800 | ps | ✔ | ||
| Duty Cycle | DC | All formats | 48 | 50 | 52 | % | ✔ |
| Period Jitter (RMS) | JPRMS | 10k samples | 1.3 | ps | ✔ (LVPECL) | ||
| Period Jitter (Pk-Pk) | JPPKPK | 10k samples | 11 | ps | ✔ (LVPECL) | ||
| Phase Jitter (RMS) | J | 1.875 MHz to 20 MHz integration bandwidth (brickwall) | 0.31 | 0.5 | ps | ✔ (LVPECL) | |
| Phase Jitter (RMS) | J | 12 kHz to 20 MHz integration bandwidth (brickwall) | 0.8 | 1.0 | ps | ✔ (LVPECL) | |
| Additive RMS Jitter Due to External Power Supply Noise | JPSR | 10 kHz sinusoidal noise | 3.0 | ps | ✔ (LVPECL) | ||
| Additive RMS Jitter Due to External Power Supply Noise | JPSR | 100 kHz sinusoidal noise | ps | ✔ (LVPECL) |
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