Frequency Stable Crystal Oscillator SKYWORKS 545BAA100M000ACGR Ultra Series with DSPLL Technology

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Product Description

Product Overview

The Skyworks Solutions Si545 Ultra Series Crystal Oscillator is an advanced, any-frequency clock generator utilizing 4th generation DSPLL technology. It delivers ultra-low jitter and low phase noise across its operating range of 0.2 to 1500 MHz with

Product Attributes

Brand: Skyworks Solutions
Technology: DSPLL
Series: Ultra Series

Technical Specifications

Parameter	Symbol	Test Condition/Comment	Min	Typ	Max	Unit
Temperature Range	TA		-40		85	C
Frequency Range (LVPECL, LVDS, CML)	FCLK		0.2		1500	MHz
Frequency Range (HCSL)	FCLK		0.2		400	MHz
Frequency Range (CMOS, Dual CMOS)	FCLK		0.2		250	MHz
Supply Voltage	VDD	3.3 V 5%	3.135	3.3	3.465	V
Supply Voltage	VDD	2.5 V 5%	2.375	2.5	2.625	V
Supply Voltage	VDD	1.8 V 5%	1.71	1.8	1.89	V
Supply Current (LVPECL, output enabled)	IDD			107	153	mA
Supply Current (LVDS/CML, output enabled)	IDD			83	121	mA
Supply Current (HCSL, output enabled)	IDD			86	126	mA
Supply Current (HCSL-Fast, output enabled)	IDD			94	138	mA
Supply Current (CMOS, output enabled)	IDD			87	127	mA
Supply Current (Dual CMOS, output enabled)	IDD			92	141	mA
Supply Current (Tristate, output disabled)	IDD			73	112	mA
Frequency Stability (Grade A)		Temperature Stability	-20		20	ppm
Frequency Stability (Grade B)		Temperature Stability	-10		10	ppm
Frequency Stability (Grade C)		Temperature Stability	-7		7	ppm
Total Stability (Grade A)	FSTAB		-50		50	ppm
Total Stability (Grade B)	FSTAB		-25		25	ppm
Total Stability (Grade C)	FSTAB		-20		20	ppm
Rise/Fall Time (LVPECL/LVDS/CML, 20%-80% VPP)	TR/TF				350	ps
Rise/Fall Time (CMOS / Dual CMOS, CL = 5 pF, 20%-80% VPP)	TR/TF			0.5	1.5	ns
Rise/Fall Time (HCSL, FCLK >50 MHz, 20%-80% VPP)	TR/TF				550	ps
Rise/Fall Time (HCSL-Fast, FCLK >50 MHz, 20%-80% VPP)	TR/TF				275	ps
Duty Cycle	DC	All formats	45		55	%
Output Enable VIH			0.7 VDD			V
Output Enable VIL					0.3 VDD	V
Output Disable Time (FCLK > 10 MHz)	TD				3	s
Output Enable Time (FCLK > 10 MHz)	TE				20	s
Powerup Time	tOSC	Time from 0.9 VDD until output frequency (FCLK) within spec			10	ms
Powerup VDD Ramp Rate	VRAMP	Fastest VDD ramp rate allowed on startup			100	V/ms
Phase Jitter (RMS, 12kHz - 20MHz) (3.2 x 5 mm, All Differential Formats)	J	FCLK 200 MHz		80	110	fs
Phase Jitter (RMS, 12kHz - 20MHz) (3.2 x 5 mm, All Differential Formats)	J	100 MHz FCLK		100	150	fs
Phase Jitter (RMS, 12kHz - 20MHz) (2.5 x 3.2 mm, All Differential Formats)	J	FCLK 200 MHz		90	130	fs
Phase Jitter (RMS, 12kHz - 20MHz) (CMOS / Dual CMOS Formats)	J	10 MHz FCLK 250 MHz		200		fs
Spurs Induced by External Power Supply Noise (LVDS, 156.25 MHz Output, 50 mVpp Ripple)	PSNR	100 kHz sine wave		-83		dBc
Package Options			2.5x3.2 mm	3.2x5 mm	5x7 mm
Total Stability (includes temp, initial accuracy, load pulling, VDD variation, and 20 yr aging at 70 C)	FSTAB	Grade A	-50		50	ppm
Total Stability (includes temp, initial accuracy, load pulling, VDD variation, and 20 yr aging at 70 C)	FSTAB	Grade B	-25		25	ppm
Total Stability (includes temp, initial accuracy, load pulling, VDD variation, and 20 yr aging at 70 C)	FSTAB	Grade C	-20		20	ppm