Backlighting system controller Broadcom ADJD-J823 with CIE Yxy input color format and 12 bit PWM resolution
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Product Description
Product Overview
The Agilent ADJD-J823 is a CMOS mixed-signal integrated circuit designed as an optical feedback device for RGB LED-based backlighting systems. It features integrated RGB photosensors, an analog-to-digital converter, color data processing logic, and a 12-bit PWM output generator. This controller samples light output, processes color information, and adjusts RGB LED output to achieve target colors, ensuring color stability over time and temperature. It supports color specification via the CIE color space through a serial interface and offers adjustable light sensitivity. The device is ideal for LCD backlighting applications.
Product Attributes
- Brand: Agilent
- Model: ADJD-J823
Technical Specifications
| Feature | Value | Units |
|---|---|---|
| Interface | 100kHz serial interface | |
| Input color format | CIE Yxy | |
| Output PWM frequency (nominal) | 6.35 | kHz |
| Output PWM resolution | 12 | bits |
| Digital Supply (nominal) | 2.6 | V |
| Analog Supply (nominal) | 2.6 | V |
| Free air operating temperature | 0 to 70 | C |
| Digital supply voltage (DVDD) | 2.5 to 3.6 | V |
| Analog supply voltage (AVDD) | 2.5 to 3.6 | V |
| Output current load high (IOH) | 3 | mA |
| Output current load low (IOL) | 3 | mA |
| Input voltage high level (VIH) | 0.7VDDD | VDDD |
| Input voltage low level (VIL) | 0 to 0.3VDDD | V |
| Power supply ramp period (tVDD_RAMP) | 100 | ms |
| Storage temperature (TSTG_ABS) | -40 to 85 | C |
| Digital supply voltage (VDDD_ABS) | -0.5 to 3.7 | V |
| Analog supply voltage (VDDA_ABS) | -0.5 to 3.7 | V |
| Input voltage (VIN_ABS) | -0.5 to VDDD+0.5 | V |
| Solder Reflow Peak temperature (TL_ABS) | 235 | C |
| Human Body Model ESD rating (ESD HBM_ABS) | 2 | kV |
| Output voltage high level (VOH) | VDDD-0.8 to VDDD-0.4 | V |
| Output voltage low level (VOL) | 0.2 to 0.4 | V |
| Dynamic supply current (IDD_DYN) | 9.4 to 14 | mA |
| Static supply current (IDD_STATIC) | 2.7 to 6 | mA |
| Sleep-mode supply current (IDD_SLP) | 0.2 to 15 | uA |
| Input leakage current (ILEAK) | -10 to 10 | uA |
| Internal clock frequency (fCLK) | 16 to 38 | MHz |
| Sensor operating detection range (EV) | 800 to 10000 | Lux |
| SCL clock frequency (fscl) | 0 to 100 | kHz |
| START condition hold time (tHD:STA) | 4 | s |
| Data hold time (tHD:DAT) | 0 to 3.45 | s |
| SCL clock low period (tLOW) | 4.7 | s |
| SCL clock high period (tHIGH) | 4.0 | s |
| Repeated START condition setup time (tSU:STA) | 4.7 | s |
| Data setup time (tSU:DAT) | 250 | ns |
| STOP condition setup time (tSU:STO) | 4.0 | s |
| Bus free time (tBUF) | 4.7 | s |
| Slave address | 0x58 | (7-bits) |
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