Transient Spike Rugged MOS Capacitor 470pF 50V Dielectric Passivation Single Layer Chip For ESD Overvoltage Protection
HACC471S50V402 Transient-Spike-Rugged MOS Capacitor — 470 pF 50 V Single Layer Chip with Dielectric Passivation
The HACC471S50V402 is a 470 pF ±10% single-layer MOS (metal-oxide-semiconductor) capacitor rated at 50 V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous thermal SiO2 dielectric and TiW-Au / TiW-Pt-Au metallization. A MOS capacitor is a single-layer capacitor formed by a metal-oxide-semiconductor structure (thermal silicon dioxide grown on a conductive silicon substrate), valued in RF and power hybrid circuits for its low ESL, stable capacitance and high insulation resistance.
This device is designed for hybrid microcircuits and power modules exposed to repetitive voltage transients and humid operating environments, where stable capacitance, high insulation resistance and arc-over-free operation under DC bias are required. Standard chip outline is 0.60 mm × 0.60 mm × 0.18 mm (±25 µm); custom capacitance, voltage rating, die geometry and metallization are available on request.
Transient Voltage Spike Ruggedness — Verified by ESD and DWV Testing
Overvoltage robustness of a MOS capacitor is defined by measurable, production-verified parameters. The HACC471S50V402 is qualified and 100% production tested as follows:
- ESD withstand voltage >2 kV HBM (Class 2 per JESD22-A114) for handling and assembly ESD events;
- Dielectric withstanding voltage (DWV) 125 V DC (250% of rated voltage, 5 s dwell), tested on 100% of production parts;
- Step-edge dielectric passivation suppresses arc-over and surface flashover between top and bottom electrodes under high DC bias and reduced-pressure operation;
- Capacitance shift below 2% and no delamination after 500 temperature cycles from -65°C to +150°C (ΔT = 215°C);
- Insulation resistance remains stable at rated voltage after repeated transient stress and thermal cycling.
Electrical Characteristics (typical, 25°C unless noted)
| Nominal Capacitance | 470 pF ±10% (1 kHz, 1.0 Vrms); tighter tolerance ±5% or matched sets on custom orders |
| Rated Voltage | 50 V DC |
| Dielectric Withstanding Voltage | 125 V DC (250% rated, 5 s, 100% tested) |
| Temperature Coefficient (TCC) | +35 ppm/°C over -55°C to +200°C |
| Dissipation Factor | ≤0.15% at 1 kHz, 1.0 Vrms |
| Q Factor | >2000 at 1 MHz; >200 at 1 GHz |
| ESR at 1 GHz | <0.1 Ω |
| Intrinsic Chip ESL | <0.05 nH (de-embedded); chip-level SRF >1 GHz for 470 pF |
| Leakage Current | <10 nA at 25°C; <500 nA at 200°C (at rated voltage) |
| Insulation Resistance | ≥104 MΩ at rated voltage, 25°C |
| ESD Tolerance | >2 kV HBM, Class 2 per JESD22-A114 |
| Operating / Storage Temperature | -55°C to +200°C / -65°C to +150°C |
| Standard Die Size | 0.60 × 0.60 × 0.18 mm (±25 µm); custom geometry, aspect ratio up to 4:1 |
| Metallization | TiW-Au top (≥2.5 µm Au, wire bondable); TiW-Pt-Au backside for AuSn eutectic / conductive epoxy |
Typical Applications
DC bias decoupling and transient suppression in GaN and SiC gate driver stages; snubber and clamp networks of motor drives and industrial power converters; RF power amplifier bias networks; outdoor wireless and base-station modules exposed to humidity; avionics and satellite payload hybrid microcircuits requiring transient and moisture robustness.
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