MOS Capacitors

Custom MOS Capacitor Pinhole Free Glassivation Passivation Wafer Level S Parameter Consistency Fine Capacitance Step HACC-CUSTOM-GS: Pinhole-Free Glassivation MOS Capacitor with Wafer-Level S-Parameter Consistency & Fine Capacitance Step Advanced Pinhole-Free Glassivation & Passivation MOS capacitor reliability in harsh environments — particularly high-humidity, high-temperature operating conditions — is dominated by the quality of the passivation and glassivation layers. A

Custom MOS Capacitor Ultra Low ESR Multi Gigabit Fine Capacitance Step Precision Tuning Wire Bond Optimized Surface HACC-CUSTOM-ES: Ultra-Low ESR MOS Capacitor for Multi-Gigabit SERDES with Fine Capacitance Step & Wire-Bond Optimized Surface Engineered Ultra-Low ESR for Multi-Gigabit Links Multi-gigabit SERDES (Serializer/Deserializer) DC blocking capacitors face stringent equivalent series resistance (ESR) requirements. At 10 Gbps and beyond, even 0.1 Ohm of ESR contributes

Custom MOS Capacitor Rad Hard Radiation Hardened Space Flat Q Response Digital Wafer Map Automated Sorting HACC101S10V500: Radiation-Hardened MOS Capacitor for Space with Digital Wafer Map & Flat-Q Response Radiation-Hardened Formulations for Space The HACC101S10V500 is specifically designed and qualified for space environments where total ionizing dose (TID) radiation degrades standard MOS structures. The radiation-hardened gate oxide — using nitrided SiO₂ or hardened Al₂O₃

Custom MOS Capacitor Eutectic Backside Metallization Flat Q Response Ultra Low Dielectric Absorption HACC-CUSTOM-BM: Eutectic-Optimized MOS Capacitor with Flat-Q Response & Ultra-Low Dielectric Absorption Customized Backside Metallization for Eutectic Soldering The HACC-CUSTOM-BM offers customer-selectable backside metallization stacks optimized for eutectic die attach processes. Three gold-based eutectic alloy systems are available, selected based on your assembly thermal

Custom MOS Capacitor Dielectric Thickness Extreme Voltage Wafer Level Gel Pak Delivery Doping Resistivity Control HACC-CUSTOM-DV: Extreme-Voltage MOS Capacitor with Flexible Wafer-Level & Gel-Pak Delivery Customized Dielectric Thickness for Extreme Voltages The HACC-CUSTOM-DV extends the single-layer MOS capacitor voltage range through engineered dielectric thickness. The standard thermally grown SiO₂ dielectric (50–5000Å) supports rated voltages up to 500V. For higher

Custom MOS Capacitor Substrate Doping Resistivity Control Array Layouts Irregular Die Geometry Binary Capacitor Arrays HACC100S10V101: Substrate-Engineered MOS Capacitor with Binary Arrays & Irregular Die Geometry Tailored Substrate Doping & Resistivity Control The HACC100S10V101 offers customization of the silicon substrate electrical properties as a design parameter — not a fixed foundry default. N+ or P+ doping profiles are tailored to achieve target resistivity from 0.001

The HACC100S10V101 is a 10pF 100V Single-Sided Bordered Single Layer Ceramic Capacitor (SLC) designed for customers requiring flexible customization, rapid prototyping turnaround, and full regulatory compliance documentation. With configurable capacitance tolerance (±10% standard, ±5% available), dielectric options (Class I COG/NPO or Class II X7R), and supported by rapid wafer-level prototyping with 3-4 week lead times, this capacitor accelerates RF module development from concept to qualification. Full RoHS, REACH, and halogen-free compliance documentation is provided per production lot. The TiW-Au (≥2.5µm) top and TiW-Pt-Au (≥2.5µm) bottom electrodes ensure reliable wire bonding and universal die-attach compatibility with epoxy, AuSn eutectic, and sintered-Ag processes.

The HACC100S10V101 is a 10pF 100V Single-Sided Bordered Single Layer Ceramic Capacitor (SLC) featuring TiW-Au (≥2.5µm Au) top and TiW-Pt-Au (≥2.5µm Au) bottom metallization for diverse mounting compatibility. The guard-ring and edge passivation design suppresses surface leakage currents, while the single-layer coaxial architecture delivers high power handling with ultra-low PIM (Passive Intermodulation). ESR below 0.1Ω at 1GHz ensures minimal insertion loss in high-frequency signal paths. Operating from -55°C to +125°C with 250% rated DWV margin (100V→250V), this device is engineered for 5G mmWave, GaN power amplifier bypass, and satellite communication applications requiring reliable performance under demanding conditions.

The HACC101S10V500 is a 100pF 50V ultra-miniature single-layer MOS capacitor featuring high breakdown voltage exceeding 125V (>2.5x rated) and ultra-low leakage current below 10nA at rated voltage. Fabricated on high-resistivity silicon substrate with thermally-grown SiO2 dielectric and 2.5μm minimum gold metallization, the wire-bondable top electrode supports thermosonic Au ball bonding and Al wedge bonding with >6gf pull strength. Packaged in an ultra-compact 0.50×0.50×0.15mm chip, this device enables high-density integration in hybrid microcircuits, phased-array T/R modules, and space-constrained RF front-end assemblies. Backside TiW-Pt-Au metallization with Pt barrier ensures compatibility with silver epoxy and AuSn eutectic die attach.

The HACC101S10V500 is a 100pF 50V single-layer MOS capacitor fabricated on high-resistivity silicon substrate with thermally-grown SiO2 dielectric and 2.5μm gold metallization. Delivering Q factor exceeding 2000 at 1MHz and maintaining Q above 200 at 1GHz, this device achieves exceptionally low ESR below 0.1Ω for minimal insertion loss in RF signal paths. With TCC below 30ppm/°C and VCC below 50ppm/V, capacitance remains stable across the full -55°C to +125°C operating range. Designed for broadband DC blocking, RF coupling, and impedance matching in microwave circuits from 1MHz to 20GHz.

HACC102S50V300 Nanoscale Staggered Guard-Ring MOS Capacitor — 1000pF 50V Single Layer Chip Product overview: The HACC102S50V300 is a single-layer metal-oxide-semiconductor (MOS) capacitor with a nominal capacitance of 1000pF (1nF) ±10% and a 50V DC working voltage. It uses a 300nm thermal silicon dioxide (SiO2 ) dielectric on a float-zone silicon substrate with a TiW-Au metallization stack. Its defining feature is a nanoscale staggered guard-ring around the top electrode,

HACC221S50V300 Phonon Scattering Control MOS Capacitor — 220pF 50V Single Layer RF Chip Product overview: The HACC221S50V300 is a single-layer metal-oxide-semiconductor (MOS) capacitor with a nominal capacitance of 220pF ±10% and a 50V DC working voltage. It is built on a high-conductivity float-zone silicon substrate with a 300nm thermal silicon dioxide (SiO2 ) dielectric and a TiW-Au metallization stack. Its defining characteristic is phonon scattering control — the

HACC471S50V200 Optimized Dielectric Relaxation Time MOS Capacitor — 470pF 50V Single Layer Chip Product overview: The HACC471S50V200 is a single-layer metal-oxide-semiconductor (MOS) capacitor with a nominal capacitance of 470pF ±10% and a 50V DC working voltage. It uses a 300nm thermal silicon dioxide (SiO2 ) dielectric on a float-zone silicon substrate with a TiW-Au metallization stack. It is engineered around two properties: an optimized dielectric relaxation time and

HACC101S50V200 Zero-TCESR MOS Capacitor — 100pF 50V Single Layer RF Chip Product overview: The HACC101S50V200 is a single-layer metal-oxide-semiconductor (MOS) capacitor with a nominal capacitance of 100pF ±10% and a 50V DC working voltage. It is built on a float-zone silicon substrate with a 300nm thermal silicon dioxide (SiO2 ) dielectric and a TiW-Au metallization stack. Its defining property is a Zero-TCESR design — the temperature coefficient of equivalent series

High Thermal Conductivity Silicon Substrate MOS Capacitor — 220 pF / 50 V (HACC221S50V500) What Is a High Thermal Conductivity Silicon Substrate MOS Capacitor? The HACC221S50V500 is a single layer MOS capacitor fabricated on a high thermal conductivity silicon substrate with a thermally grown SiO2 dielectric. It is designed to conduct heat away from the active die instead of trapping it, which keeps the capacitor cooler and more stable during continuous RF power operation. It

Self-Healing Dielectric Single Layer MOS Capacitor — 330 pF / 50 V (HACC331S50V150) What Is a Self-Healing Dielectric MOS Capacitor? The HACC331S50V150 is a single layer MOS (metal-oxide-semiconductor) capacitor that uses a thermally grown silicon dioxide (SiO2) dielectric on a float-zone silicon substrate. Its self-healing dielectric design isolates a localized breakdown site so that a transient overvoltage does not develop into a permanent short circuit. It is a wire

HACC101S200V801 Low Quantum Capacitance MOS Capacitor 100pF 200V Single Layer Wire Bondable RF Chip Product definition: The HACC101S200V801 is a single-layer metal-oxide-semiconductor (MOS) capacitor built on a high-resistivity float-zone silicon substrate with a dense, thermally grown silicon dioxide (SiO2 ) dielectric. It delivers 100 pF (±10%) at a 200 V DC working voltage in a 0.50 mm × 0.50 mm × 0.15 mm wire-bondable chip. The same device family is also described as a

HACC471S100V701 Symmetrical Dual-Polarity MOS Capacitor 470pF 100V Single Layer Wire Bondable RF Chip Product definition: The HACC471S100V701 is a single-layer metal-oxide-semiconductor (MOS) capacitor built on a high-resistivity float-zone silicon substrate with a thermally grown silicon dioxide (SiO2 ) dielectric. It delivers 470 pF (±10%) at a 100 V DC working voltage in a 0.50 mm × 0.50 mm × 0.15 mm wire-bondable chip. The same device family is also described as a single

HACC471S100V701 MOS Capacitor — 470 pF 100 V with Oxygen-Free Ohmic Contact and Low-ESR Energy Discharge The HACC471S100V701 is a 470 pF ±10% single-layer MOS capacitor rated at 100 V DC, fabricated on a conductive silicon substrate with an oxygen-free pure-gold ohmic backside contact. By eliminating interfacial oxide at the backside metal-to-silicon junction, the device achieves low interfacial and series resistance, which directly improves discharge efficiency in energy

HACC102T50V601 Deep-Trench MOS Capacitor — 1000 pF 50 V High-Density Single Layer Chip with Bias-Stable Dielectric The HACC102T50V601 is a 1000 pF ±10% single-layer MOS capacitor rated at 50 V DC, built on a 3D deep-trench silicon architecture in which deep trenches etched into the silicon substrate multiply the effective electrode area within the same die footprint. The capacitor delivers 1000 pF in a 0.50 mm × 0.50 mm die; for reference, planar 1000 pF MOS capacitors in