• Simultaneous Read and Write Sigma Quad™ Interface
• JEDEC-standard pin out and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 144 Mb devices
• 13 mm x 15 mm, 165 FPBGA
• RoHS-compliant 165-bump BGA package available
• 64MB or 72MB product family
• Default to SCD x36 Interleaved Pipeline mode

Simultaneous Read and Write SigmaQuad™ Interface• JEDEC-standard pinout and package• Dual

Double Data Rate interface• Byte Write controls sampled at data-in time• Burst of 4 Read and Write•

1.8 V +100/–100 mV core power supply• 1.5 V or 1.8 V HSTL Interface• Pipelined read operation• Fully coherent

read and write pipelines• ZQ pin for programmable output drive strength• IEEE 1149.1 JTAG-compliant Boundary

Scan• Pin-compatible with present 144 Mb devices• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package•

RoHS-compliant 165-bump BGA package availableSigmaQuad™ Family OverviewThe GS8662D08/09/18/36BD

are built in compliance withthe SigmaQuad-II SRAM pinout standard for Separate I/Osynchronous SRAMs.

They are 75,497,472-bit (72Mb)SRAMs. The GS8662D08/09/18/36BD SigmaQuad SRAMsare just one element in

a family of low power, low voltageHSTL I/O SRAMs designed to operate at the speeds needed toimplement

economical high performance networking systems.