AEC Q101 certified automotive P channel MOSFET RENESAS NP50P04SDG E1 AY with low on state resistance
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Product Description
Product Overview
This P-channel MOS Field Effect Transistor (NP50P04SDG) is designed for high current switching applications, particularly in the automotive sector. It offers super low on-state resistance and low input capacitance, making it suitable for demanding automotive applications. The product is AEC-Q101 qualified and Pb-free.
Product Attributes
- Brand: Renesas Electronics
- Certifications: AEC-Q101 Qualified
- Material: Pb-free (external electrode)
- Application: Automotive
Technical Specifications
| Item | Symbol | Min | Typ | Max | Unit | Test Conditions |
| Drain to Source Voltage (VGS = 0 V) | VDSS | -40 | V | |||
| Gate to Source Voltage (VDS = 0 V) | VGSS | ±20 | V | |||
| Drain Current (DC) (Tc = 25 °C) | ID(DC) | ±50 | A | |||
| Drain Current (pulse) | ID(pulse) | ±150 | A | Notes1 | ||
| Total Power Dissipation (Tc = 25 °C) | PT1 | 84 | W | |||
| Total Power Dissipation (Ta = 25 °C) | PT2 | 1.2 | W | |||
| Channel Temperature | Tch | 175 | °C | |||
| Storage Temperature | Tstg | -55 | 175 | °C | ||
| Single Avalanche Current | IAS | 37 | A | Notes2 | ||
| Single Avalanche Energy | EAS | 136 | mJ | Notes2 | ||
| Zero Gate Voltage Drain Current | IDSS | -10 | µA | VDS = -40 V, VGS = 0 V | ||
| Gate Leakage Current | IGSS | ±100 | nA | VGS = ±20 V, VDS = 0 V | ||
| Gate to Source Threshold Voltage | VGS(th) | -1.0 | -1.6 | -2.5 | V | VDS = VGS, ID = -250µA |
| Forward Transfer Admittance | | yfs | | 15 | 33 | S | VDS = -10 V, ID = -25 A (Notes4) | |
| Drain to Source On-state Resistance | RDS(on)1 | 7.7 | 9.6 | mΩ | VGS = -10 V, ID = -25 A (Notes4) | |
| Drain to Source On-state Resistance | RDS(on)2 | 9.3 | 15 | mΩ | VGS = -4.5 V, ID = -25 A (Notes4) | |
| Input Capacitance | Ciss | 5000 | pF | VDS = -10 V, VGS = 0 V, f = 1 MHz | ||
| Output Capacitance | Coss | 770 | pF | VDS = -10 V, VGS = 0 V, f = 1 MHz | ||
| Reverse Transfer Capacitance | Crss | 420 | pF | VDS = -10 V, VGS = 0 V, f = 1 MHz | ||
| Turn-on Delay Time | td(on) | 13 | ns | VDD = -20 V, ID = -25 A, VGS = -10 V, RG = 0 Ω | ||
| Rise Time | tr | 13 | ns | VDD = -20 V, ID = -25 A, VGS = -10 V, RG = 0 Ω | ||
| Turn-off Delay Time | td(off) | 405 | ns | VDD = -20 V, ID = -25 A, VGS = -10 V, RG = 0 Ω | ||
| Fall Time | tf | 180 | ns | VDD = -20 V, ID = -25 A, VGS = -10 V, RG = 0 Ω | ||
| Total Gate Charge | Qg | 100 | nC | VDD = -32 V, VGS = -10 V, ID = -50 A | ||
| Gate to Source Charge | Qgs | 12 | nC | VDD = -32 V, VGS = -10 V, ID = -50 A | ||
| Gate to Drain Charge | Qgd | 28 | nC | VDD = -32 V, VGS = -10 V, ID = -50 A | ||
| Body Diode Forward Voltage | VF(S-D) | 0.95 | 1.5 | V | IF = -50 A, VGS = 0 V (Notes4) | |
| Reverse Recovery Time | trr | 48 | ns | IF = -50 A, VGS = 0 V, di/dt = -100 A/µs | ||
| Reverse Recovery Charge | Qrr | 66 | nC | IF = -50 A, VGS = 0 V, di/dt = -100 A/µs | ||
| Channel to Case Thermal Resistance | Rth(ch-c) | 1.78 | °C/W | Notes3 | ||
| Channel to Ambient Thermal Resistance | Rth(ch-a) | 125 | °C/W | Notes3 |
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Sellina