P channel Power MOS FET RENESAS NP100P06PLG E1 AY with Low On State Resistance and Gate Protection
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Product Description
Product Overview
This P-channel Power MOS FET is designed for high current switching applications, offering super low on-state resistance and low input capacitance. It features built-in gate protection and is designed for automotive applications, meeting AEC-Q101 qualifications. The product is Pb-free.
Product Attributes
- Brand: Renesas Electronics
- Certifications: AEC-Q101 qualified
- Material: Pb-free (external electrode)
- Application: Automotive
Technical Specifications
| Item | Symbol | Min | Typ | Max | Unit | Test Conditions |
| Drain to Source Voltage (VGS = 0 V) | VDSS | -60 | V | |||
| Gate to Source Voltage (VDS = 0 V) | VGSS | 20 | V | |||
| Drain Current (DC) (Tc = 25 C) | ID(DC) | -100 | A | |||
| Drain Current (pulse) | ID(pulse) | -300 | A | Notes1 | ||
| Total Power Dissipation (Tc = 25 C) | PT1 | 200 | W | |||
| Total Power Dissipation (Ta = 25 C) | PT2 | 1.8 | W | |||
| Channel Temperature | Tch | 175 | C | |||
| Storage Temperature | Tstg | -55 | 175 | C | ||
| Single Avalanche Current | IAS | 64 | A | Notes2 | ||
| Single Avalanche Energy | EAS | 420 | mJ | Notes2 | ||
| Channel to Case Thermal Resistance | Rth(ch-c) | 0.75 | C/W | Notes3 | ||
| Channel to Ambient Thermal Resistance | Rth(ch-a) | 83.3 | C/W | Notes3 | ||
| Zero Gate Voltage Drain Current | IDSS | -10 | A | VDS = -60 V, VGS = 0 V | ||
| Gate Leakage Current | IGSS | 10 | A | VGS = 20 V, VDS = 0 V | ||
| Gate to Source Threshold Voltage | VGS(th) | -1.0 | -1.6 | -2.5 | V | VDS = -10 V, ID = -1 mA |
| Forward Transfer Admittance | |yfs| | 43 | 86 | S | VDS = -10 V, ID = -50 A (Notes4) | |
| Drain to Source On-state Resistance | RDS(on)1 | 4.4 | 6.0 | m | VGS = -10 V, ID = -50 A (Notes4) | |
| Drain to Source On-state Resistance | RDS(on)2 | 5.0 | 7.8 | m | VGS = -4.5 V, ID = -50 A (Notes4) | |
| Input Capacitance | Ciss | 15000 | pF | VDS = -10 V, VGS = 0 V, f = 1 MHz | ||
| Output Capacitance | Coss | 1810 | pF | VDS = -10 V, VGS = 0 V, f = 1 MHz | ||
| Reverse Transfer Capacitance | Crss | 840 | pF | VDS = -10 V, VGS = 0 V, f = 1 MHz | ||
| Turn-on Delay Time | td(on) | 28 | ns | VDD = -30 V, ID = -50 A, VGS = -10 V, RG = 0 | ||
| Rise Time | tr | 35 | ns | VDD = -30 V, ID = -50 A, VGS = -10 V, RG = 0 | ||
| Turn-off Delay Time | td(off) | 275 | ns | VDD = -30 V, ID = -50 A, VGS = -10 V, RG = 0 | ||
| Fall Time | tf | 100 | ns | VDD = -30 V, ID = -50 A, VGS = -10 V, RG = 0 | ||
| Total Gate Charge | Qg | 300 | nC | VDD = -48 V, VGS = -10 V, ID = -100 A | ||
| Gate to Source Charge | Qgs | 35 | nC | VDD = -48 V, VGS = -10 V, ID = -100 A | ||
| Gate to Drain Charge | Qgd | 85 | nC | VDD = -48 V, VGS = -10 V, ID = -100 A | ||
| Body Diode Forward Voltage | VF(S-D) | 0.92 | 1.5 | V | IF = -100 A, VGS = 0 V (Notes4) | |
| Reverse Recovery Time | trr | 70 | ns | IF = -100 A, VGS = 0 V, di/dt = -100 A/s | ||
| Reverse Recovery Charge | Qrr | 135 | nC | IF = -100 A, VGS = 0 V, di/dt = -100 A/s |
Notes: 1. PW 10 s, Duty Cycle 1%. 2. Starting Tch=25, VDD = -30V, RG = 25 , VGS = -20 0V, L = 100H. 3. Designed target value on Renesas measurement condition. Not subject to production test. 4. Pulse test.
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