MOS Capacitors

HACC221S100V502 Precision MOS Capacitor — 220 pF 100 V with Sub-1% Capacitance Matching and CTE Optimization for GaN & SiC Power Substrates The HACC221S100V502 is a 220 pF ±10% single-layer MOS (metal-oxide-semiconductor) capacitor rated at 100 V DC, fabricated on float-zone silicon (>1000 Ω·cm) with 300 nm-class thermal SiO2 dielectric and TiW-Au / TiW-Pt-Au metallization. Standard chip outline is 0.55 mm × 0.55 mm × 0.18 mm (±25 µm). It is engineered for wide-bandgap power

HACC471S50V402 Transient-Spike-Rugged MOS Capacitor — 470 pF 50 V Single Layer Chip with Dielectric Passivation The HACC471S50V402 is a 470 pF ±10% single-layer MOS (metal-oxide-semiconductor) capacitor rated at 50 V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous thermal SiO2 dielectric and TiW-Au / TiW-Pt-Au metallization. A MOS capacitor is a single-layer capacitor formed by a metal-oxide-semiconductor structure (thermal silicon dioxide grown on a

HACC101S50V601 100pF 50V MOS Capacitor Ultra Low Total Harmonic Distortion Zero Dielectric Dispersion Paraelectric SiO2 Single Layer Chip The HACC101S50V601 is a 100pF ±10% single-layer MOS capacitor rated at 50V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous paraelectric thermal SiO2 dielectric and TiW-Au / TiW-Pt-Au metallization. Standard chip dimensions are 0.50mm × 0.50mm × 0.15mm (±25µm). Because thermal SiO2 is paraelectric (no ferroelectric

HACC102S100V301 1000pF 100V MOS Capacitor Advanced Dielectric Passivation Step Edge Geometry Moisture Resistant Single Layer Chip The HACC102S100V301 is a 1000pF ±10% single-layer MOS capacitor rated at 100V DC, fabricated on float-zone silicon (>1000 Ω·cm) with an amorphous thermal SiO2 dielectric and TiW-Au / TiW-Pt-Au metallization. Standard chip dimensions are 0.75mm × 0.75mm × 0.20mm (±25µm), with custom capacitance, voltage rating, die geometry (aspect ratio up to 4:1),

HACC101S30V200 Extreme High-Temperature MOS Capacitor: 100pF 30V with 200°C Continuous Operation and Superior ESD Tolerance The HACC101S30V200 is a 100pF ±10% single-layer MOS capacitor rated at 30V DC, engineered for continuous operation at temperatures up to 200°C—substantially exceeding the industry-standard 125°C limit for conventional MOS capacitors. Fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric, this device incorporates a

HACC500S50V500 Custom Low Dissipation Factor MOS Capacitor 50pF 50V Minimal Tan δ Under RF Power — Fully Customizable Metal Layout & Geometry The HACC500S50V500 is a fully customizable 50 pF 50 V single-layer MOS capacitor featuring industry-leading low dissipation factor (tan δ < 0.001 at 1 GHz) verified under full RF power excitation up to +40 dBm (10 W) continuous wave . With a fully configurable metal layout—including selective gold thickness, patterned multi-pad

HACC102S80V500 Zero Dielectric Memory MOS Capacitor: 1000pF 80V with Ultra-Linear C-V Characteristics and Paraelectric SiO2 Dielectric The HACC102S80V500 is a 1000pF ±10% single-layer MOS capacitor rated at 80V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown paraelectric SiO2 dielectric. Chip dimensions are 0.75mm × 0.75mm × 0.15mm with TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au, Pt barrier). This device is

HACC470S50V160 Ultra-Small Radiation Hardened MOS Capacitor 47pF 50V Zero Piezoelectric Noise Bare Die Chip The HACC470S50V160 is a 47pF ±10% single-layer MOS capacitor rated at 50V DC, fabricated on high-resistivity float-zone silicon (>1000 Ω·cm) with 300nm thermally-grown amorphous SiO₂ dielectric. With an ultra-miniature footprint of just 0.40 * 0.40 * 0.15mm (16mil * 16mil * 6mil) — a 36% area reduction versus standard 0.50mm chips — this device enables capacitor

HACC471S20V500 Custom High Q Ultra-Low ESL MOS Capacitor 470pF 20V Wire-Bondable Single Layer Chip The HACC471S20V500 is a high-performance, fully customizable Single Layer MOS capacitor fabricated on high-resistivity float-zone silicon substrate (>1000 Ohm·cm) with 300nm thermally-grown SiO2 dielectric. Rated at 470pF ±10% with 20V DC continuous operating voltage, this device combines High Q factor , Ultra-Low ESL/ESR , Exceptional Capacitance Stability , and Wire-Bondable

HACC331S25V500 Custom High-K Dielectric MOS Capacitor 330pF 25V Ultra-Low Phase Noise for VCO & PLL Circuits — Fully Customizable The HACC331S25V500 is a fully customizable 330 pF 25 V single-layer MOS capacitor featuring an engineered high-K composite dielectric stack (SiO&sub2;/Al&sub2;O&sub3;/HfO&sub2;) that achieves 1,320 pF/mm² areal capacitance density —over 3× the density of conventional SiO&sub2;-only MOS capacitors—while delivering ultra-low phase noise below -16

HACC221S30V120 Miniaturized High-Density MOS Capacitor: 220pF 30V with Exceptional High-Frequency Stability and Wafer-Level Customization The HACC221S30V120 is a 220pF ±10% single-layer MOS capacitor rated at 30V DC, fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric. With an ultra-miniature footprint of just 0.35 x 0.35 x 0.15mm — a 51% area reduction versus standard 0.50mm chips — this device achieves an industry-leading capacitance

HACC102S80V750 Custom High Breakdown Voltage MOS Capacitor 1000pF 80V Ultra-Stable TCC Low Leakage Wire-Bondable Chip The HACC102S80V750 is a high-reliability, fully customizable Single Layer MOS capacitor engineered for applications demanding High Breakdown Voltage , Ultra-Low Leakage Current , and Exceptional Capacitance Stability over Temperature and Voltage . Fabricated on high-resistivity float-zone silicon substrate (>1000 Ohm·cm) with 300nm thermally-grown SiO2

HACC-100S30V100 Custom Multi-Capacitor Array MOS Chip 4 Channel * 100pF 30V Wafer-Level Tested Verified Low Defect Rate The HACC-100S30V100 is a fully customizable single-layer MOS multi-capacitor array integrating four independent 100pF ±10% capacitor blocks on a single 1.00 * 1.00 * 0.15mm die. Each channel features its own top electrode bond pad with independent wire-bond access, while all channels share a common backside ground plane through TiW-Pt-Au metallization.

HACC151S100V200 Ultra-Low Leakage MOS Capacitor: 150pF 100V with High Dielectric Breakdown Strength and Extreme Thermal Endurance The HACC151S100V200 is a 150pF ±10% single-layer MOS capacitor rated at 100V DC, engineered for continuous operation at temperatures up to 200°C. Fabricated on float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric, this device delivers industry-leading 250V dielectric withstanding voltage. Chip dimensions are 0.50 x 0.50 x 0

HACC101S25V500 Ultra-High Self-Resonant Frequency MOS Capacitor: 100pF 25V with Conductive Silicon Substrate for Direct Grounding The HACC101S25V500 is a 100pF ±10% single-layer MOS capacitor rated at 25V DC, fabricated on conductive float-zone silicon (>1000Ω·cm) with 300nm thermally-grown SiO2 dielectric. Chip dimensions are 0.50mm × 0.50mm × 0.15mm with TiW-Au top metallization (2.5µm minimum Au) and TiW-Pt-Au backside (1.0µm minimum Au). This device is engineered for

220pF 15V single-layer MOS capacitor with 1.5A RMS current handling, zero dielectric aging for unlimited shelf life, and ultra-high SRF. 0.50mm chip with 880pF/mm² density for RF power amplifier bypass and long-lifecycle programs.

100pF 15V single-layer MOS capacitor with silicon CTE matching to alumina/AlN/CuMo, ultra-high SRF >2.2GHz, and dual backside metallization options (TiW-Pt-Au for epoxy/solder, Au-only for eutectic). 0.50mm chip for hybrid microcircuits.

100pF 20V single-layer MOS capacitor with optional AuSn eutectic pre-deposited backside for high-thermal-conductivity die attach. 0.50mm chip on float-zone silicon for RF power amplifier matching, GaN PA modules, and high-power microwave applications.

150pF 30V single-layer MOS capacitor with custom geometries up to 4:1 AR, MSL 1 moisture rating, and TiW-Au metallization. 0.50mm chip for outdoor base stations, automotive ECUs, and industrial sensing in humid environments.

100pF 30V single-layer MOS capacitor with